參數(shù)資料
型號： Eval-AD5045EBZ
廠商： Analog Devices, Inc.
英文描述： Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
中文描述： 完全準確12-/14-/16-Bit VOUT電源DAC的SPI接口的2.7 V至5.5 V采用TSSOP
文件頁數(shù)： 1/33頁
文件大小： 435K
代理商： EVAL-AD5045EBZ
Fully Accurate 12-/14-/16-Bit V
OUT
DAC SPI Interface
2.7 V to 5.5 V in a TSSOP
AD5025/45/65
Preliminary Technical Data
FEATURES
Low power Dual 12-/14-/16 bit DAC, ± 1LSB INL
Individual Voltage reference pins
Rail-to-rail operation
2.7 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V, 200 nA @ 3 V
3 power-down functions
Per channel power-down
Low glitch upon power up
Hardware Power Down lock Out Capability
Hardware LDAC with LDAC override function
CLR Function to programmable code
SDO daisy-chaining option
14 lead TSSOP
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2007 Analog Devices, Inc. All rights reserved.
www.analog.com
Functional Block Diagrams
INLOGIC
SCLK
SYNC
DIN
CLR
RINPUT
RINPUT
REDAC
REDAC
V
DD
GND
PRESET
DAC A
DAC B
BUFFER
BUFFER
V
REFA
POLOGIC
V
OUT
A
V
OUT
B
AD5025/AD5045R/AD5065
LDAC
LDAC
0
POR
SDO
V
REFB
PDL
Figure 1.AD5025/45/65
Table 1. Related Devices
Part No.
AD5666
AD5066
AD5064/44/24
AD5063/62
AD5061
AD5060/40
Description
Quad,16-bit buffered D/A,16 LSB INL, TSSOP
Quad,16-bit unbuffered D/A,1 LSB INL, TSSOP
Quad 16-bit
nano
DAC, 1 LSB INL, TSSOP
16-bit
nano
DAC, 1 LSB INL, MSOP
16-/14bit
nano
DAC, 4 LSB INL, SOT-23
16-/14bit
nano
DAC, 1 LSB INL, SOT-23
The AD5025/45/65 are low power, dual 12-/14-/16-bit buffered
voltage-out DACs offering relative accuracy specs of 1 LSB INL
with individual reference pins and can operate from a single 2.7
V to 5.5 V supply. The AD5025/45/65 64 parts also offer a
differential accuracy specification of ±1 LSB. The parts use a
versatile 3-wire, low power Schmitt trigger serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface
standards. The reference for the AD5025/45 and AD5065 are
supplied from an external pin. A reference buffer is also
provided on-chip. The AD5025/45/64 incorporates a power-on
reset circuit that ensures the DAC output powers up zero scale
or midscale and remains there until a valid write takes place to
the device. The AD5025/45/65 contain a power-down feature
that reduces the current consumption of the device to typically
330 nA at 5 V and provides software selectable output loads
while in power-down mode. The parts are put into power-down
mode over the serial interface. Total unadjusted error for the
parts is <2 mV.
Both parts exhibit very low glitch on power-up. The outputs of
all DACs can be updated simultaneously using the LDAC
function, with the added functionality of user-selectable DAC
channels to simultaneously update. There is also an
asynchronous CLR that clears all DACs to a software-selectable
code—0 V, midscale, or full scale. The Part also features a power
down lockout pin PDL, which can be used to prevent the DAC
from entering power down under any circumstances over the
serial interface.
PRODUCT HIGHLIGHTS
1.
Dual channel available in 14-lead TSSOP package with
individual Voltage reference pins.
2.
12-/14-/-16 bit accurate, 1 LSB INL.
3.
Low glitch on power-up.
4.
High speed serial interface with clock speeds up to 50 MHz.
5.
Three power-down modes available to the user.
6.
Reset to known output voltage (zero scale or midscale).
7.
Power Down lockout capability.
相關(guān)PDF資料
PDF描述
Eval-AD5065EBZ Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
EVAL-AD5066EBZ Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP
EVAL-AD5379EB 40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC
EVAL-AD5381EB 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
EVAL-AD5382EB 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD5060EB 制造商:Analog Devices 功能描述:EVAL BD FOR AD506X DAC 14-/16BIT, SERL INPUT - Bulk
EVAL-AD5060EBZ 功能描述:BOARD EVAL FOR AD5060 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5061EBZ 功能描述:BOARD EVALUATION AD5061 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5062EB 制造商:Analog Devices 功能描述:EVAL BD FOR AD506X DAC 14-/16BIT, SERL INPUT - Bulk
EVAL-AD5062EBZ 功能描述:BOARD EVAL FOR AD5062 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
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