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參數資料
| 型號： | EVAL-AD421EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Loop-Powered 4 mA to 20 mA DAC |
| 中文描述： | 回路供電4毫安到20毫安援 |
| 文件頁數： | 5/14頁 |
| 文件大?。?/td> | 171K |
| 代理商： | EVAL-AD421EB |
AD421
–
5
–
REV. C
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
REF OUT1
Reference Output 1. A precision +1.25 V reference is provided at this pin. It is intended as a precision ref-
erence source for other devices in the transmitter. REF OUT1 is a buffered output capable of providing up
to 0.5 mA to external circuitry. If REF OUT 1 is required to sink current, a resistive load of 100 k
to COM
should be added. (See Reference section.)
Reference Output 2. A precision +2.5 V reference is provided at this pin. To operate the AD421 with its
own reference, REF OUT2 should be connected to REF IN. It can also be used as a precision reference
source for other devices in the transmitter. REF OUT2 is a buffered output capable of providing up to
0.5 mA to external circuitry.
Voltage Reference Input. The reference voltage for the AD421 is applied to this pin and it sets the span for
the AD421. The nominal reference voltage for the AD421 is +2.5 V for correct operation. This can be sup-
plied using an external reference source or by using the part’s own REF OUT2 voltage.
Regulated Voltage Control Input. The LV input controls the loop gain of the servo amplifier to set V
CC
.
With LV connected to COM, the regulator voltage is set to 5 V nominal. If the LV input is connected through
0.01
μ
F to V
CC
, the regulated voltage is nominally 3.3 V. With LV connected to V
CC
the regulated voltage,
V
CC
, is 3 V nominal.
DAC Latch Input. Logic Input. A rising edge of the LATCH signal loads the data from the serial input shift
register to the DAC latch and hence updates the output of the DAC. The number of clock cycles provided
between latch pulses determines whether the DAC is in alarm or normal current mode. (See Digital Inter-
face section.)
Data Clock Input. Data on the DATA input is clocked into the shift register on the rising edge of this
CLOCK input. The period of this clock equals the input serial data bit rate. This serial clock rate can be up
to 10 MHz. If 16 clock cycles are provided between LATCH pulses then the data on the DATA input is
accepted as normal 4–20 mA data. If more than 16 clock cycles are provided between LATCH pulses, the
data is assumed to be alarm current data (see
Digital Interface
section).
Data Input. The data to be loaded to the AD421 input shift register is applied to this input. Data should be
valid on the rising edge of the CLOCK input.
Loop Return Output. LOOP RTN is the return path for current flowing in the current loop.
Common. This is the reference potential for the AD421 analog and digital inputs and outputs and for the
voltage regulator output.
Filtering Capacitor. A low dielectric absorption capacitor ceramic capacitor should be connected between
this pin and COM for internal filtering of the switched current sources.
Filtering Capacitor. See C3 description.
Filtering Capacitor. See C3 description.
Output from the Voltage Regulator Loop. The DRIVE signal controls the external pass transistor to establish and
maintain the correct V
CC
level programmed by the LV inputs while providing the necessary bias as the loop cur-
rent is programmed from 4 mA to 20 mA.
Compensation Capacitor Input. A capacitor connected between COMP and DRIVE is required to stabilize
the feedback loop formed with the regulator op amp and the external pass transistor.
This open collector pin sinks the necessary current from the loop so that the current flowing into BOOST
plus the current flowing into COM is equal to the programmed loop current.
Power Supply. V
CC
is the power supply input of the AD421 and it also provides the voltage regulator output,
driven by the external pass transistor. It is used both to bias the AD421 itself and to provide power for the
rest of the smart transmitter circuitry. The LV input determines the regulated voltage output to be either
3 V, 3.3 V or 5 V nominal. Alternatively, a separate power supply can be connected to this pin to power the
AD421. V
CC
should be decoupled to COM with a 2.2
μ
F capacitor.
2
REF OUT2
3
REF IN
4
LV
5
LATCH
6
CLOCK
7
DATA
8
9
LOOP RTN
COM
10
C3
11
12
13
C2
C1
DRIVE
14
COMP
15
BOOST
16
V
CC
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