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參數(shù)資料
| 型號： | EVAL-AD1871EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1871 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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REV. 0
AD1871
–11–
Pin Function Redefinition in External Control Mode
Pin
Input/
No.
Output
Mnemonic
Description
2I
256/512
Clock Rate Select. This pin is used to select between an MCLK of 256
fS (pin low) or
512
fS (pin high).
3I
DF0
Data Format Select 0. This pin is used as the low bit (DF0) of the data format selection
(see section on External Control).
4I
DF1
Data Format Select 1. This pin is used as the high bit (DF1) of the data format selection
(see section on External Control).
5I
M/S
Master/Slave Select. This pin is used to select between the Master (pin low) or Slave (pin
high) Modes.
Pin Function Redefinition in Modulator Mode
Pin
Input/
No.
Output
Mnemonic
Description
3O
MODCLK
This pin provides a clock output that allows the user to decode the left and right channel
modulator outputs. It is similar to a left/right clock but runs (nominally) at 5.6448 MHz
and gates a 4-bit modulator output word in each phase (see section on Modulator Mode).
25
O
D3
Bit 3 of the Modulator Output Word
26
O
D2
Bit 2 of the Modulator Output Word
27
O
D1
Bit 1 of the Modulator Output Word
28
O
D0
Bit 0 of the Modulator Output Word
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