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參數(shù)資料
型號(hào)： EVAL-AD1871EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD1871
標(biāo)準(zhǔn)包裝： 1
系列： *
AD1871
–8–
REV. 0
CONTROL INTERFACE (SPI) TIMING
Mnemonic
Description
Min
Typ
Max
Unit
Comment
tCCH
CCLK High Width
40
ns
tCCL
CCLK Low Width
40
ns
tCCP
CCLK Period
80
ns
tCDS
CDATA Setup Time
10
ns
To CCLK Rising
tCDH
CDATA Hold Time
10
ns
From CCLK Rising
tCLS
CLATCH Setup Time
10
ns
To CCLK Rising
tCLH
CLATCH Hold Time
10
ns
From CCLK Rising
tCOE
COUT Enable
15
ns
From CLATCH Falling
tCOD
COUT Delay
20
ns
From CCLK Falling
tCOTS
COUT Three-State
25
ns
From CLATCH Rising
tCCH
tCCL
CCLK
CLATCH
CIN
COUT
D15
D14
D12
D11
D10
D07
D06
D04
D03
D02
D01
D00
D13
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
D09
D05
tCHD
tCSU
tCCL
tCLH
Figure 7. Control Interface Timing
DIGITAL I/O
Parameter
Min
Typ
Max
Unit
Input Voltage High (VIH)
2.4
V
Input Voltage Low (VIL)
0.8
V
Input Leakage (IIH @ VIH = 5 V)
10
mA
Input Leakage (IIL @ VIL = 0 V)
10
mA
Output Voltage High (VOH @ IOH = –2 mA)
ODVDD – 0.4 V
V
Output Voltage Low (VOL @ IOL = +2 mA)
0.4
V
Input Capacitance
15
pF
POWER
Parameter
Min
Typ
Max
Unit
Supplies
Voltage, AVDD, and DVDD
4.5
5
5.5
V
Voltage, ODVDD
2.7
5.5
V
Analog Current
40
45
mA
Analog Current—Power-Down (MCLK Running)
4.0
6.0
mA
Digital Current, DVDD
18
22
mA
Digital Current, ODVDD
0.5
1.0
mA
Digital Current—Power-Down (MCLK Running) DVDD
*
0.8
2.0
mA
Digital Current—Power-Down (MCLK Running) ODVDD
*
1.0
15.0
mA
Power Supply Rejection
1 kHz 300 mV p-p Signal at Analog Supply Pins
–86
dB
20 kHz 300 mV p-p Signal at Analog Supply Pins
–77
dB
*RESET held low.
TEMPERATURE RANGE
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
25
∞C
Functionality Guaranteed
–40
+105
∞C
Storage
–65
+150
∞C
Specifications subject to change without notice.
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