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| 型號(hào)： | EVAL-AD1871EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1871 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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AD1871
–20–
REV. 0
The SPI compatible control port features four signals (CCLK,
CLATCH, CDATA, and COUT). The CLATCH signal is an
enable line that must be low to allow communication to or from
the control port. The CCLK is the serial clock that clocks in
serial data via the CDATA pin and clocks out serial data via the
COUT pin. Figures 20 and 21 show details of the control port
timing.
Table II. Register Address Map
Address
Control Register
0000
Control Register I
0001
Control Register II
0010
Control Register III
0011
Peak Reading Register I
0100
Peak Reading Register II
DOU T
LRCLK
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
BCLK
DOU T
LEFT CH AN N EL
BCLK
MSB
–1
MSB
–2
LSB
+1
LSB
123
2 3
24
RI GH T CH AN N EL
123
2 3
2 4
MSB
–1
MSB
–2
LSB
+1
LSB
Figure 18. Cascade Mode Data Interface Timing
CI N
CLAT CH
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
CCLK
CI N
CCLK
MSB
–1
LSB
+1
LSB
Figure 19. Cascade Mode Control Port Timing
CONTROL/STATUS REGISTERS
The AD1871’s Operating Mode is set by programming three,
10-bit Control Registers via an SPI compatible port. Table III
details the format of the AD1871 control words, which are 16
bits wide with a 4-bit address field in Positions 15 through 12,
a Read/
Write Bit in Position 11, a Reserved Bit in Position 10,
and 10 bits of register data (corresponding to the control regis-
ter width) in Positions 9 through 0. The three control words
occupy Addresses 0000b through 0010b in the register map (see
Table II).
The AD1871 also features two readback (status) registers that
can be enabled to track the peak reading on each of the chan-
nels (left and right). These 6-bit results are read back via the
SPI compatible port in a 16-bit frame similar to that of the
control words.
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