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參數(shù)資料
| 型號： | EVAL-AD1837AEB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| 中文描述： | 2的ADC，8 DAC的，96千赫，24位編解碼器 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 523K |
| 代理商： | EVAL-AD1837AEB |
REV. B
–4–
AD1837
TIMING SPECIFICATIONS
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
t
MH
t
ML
t
PDR
SPI PORT
t
CCH
t
CCL
t
CCP
t
CDS
t
CDH
t
CLS
t
CLH
t
COE
t
COD
t
COTS
DAC SERIAL PORT
Normal Mode (Slave)
t
DBH
t
DBL
f
DB
t
DLS
t
DLH
t
DDS
t
DDH
Packed 256 Modes (Slave)
t
DBH
t
DBL
f
DB
t
DLS
t
DLH
t
DDS
t
DDH
ADC SERIAL PORT
Normal Mode (Master)
t
ABD
t
ALD
t
ABDD
Normal Mode (Slave)
t
ABH
t
ABL
f
AB
t
ALS
t
ALH
Packed 256 Mode (Master)
t
PABD
t
PALD
t
PABDD
MCLK High
MCLK Low
PD
/
RST
Low
15
15
20
ns
ns
ns
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
40
40
80
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
To CCLK Rising
From CCLK Rising
To CCLK Rising
From CCLK Rising
From CLATCH Falling
From CCLK Falling
From CLATCH Rising
15
20
25
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
60
60
64 f
S
10
10
10
10
ns
ns
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
15
15
256 f
S
10
5
10
10
ns
ns
ns
ns
ns
ns
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
ABCLK Delay
ALRCLK Delay Low
ASDATA Delay
25
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
60
60
64 f
S
5
15
ns
ns
ns
ns
To ABCLK Rising
From ABCLK Rising
ABCLK Delay
LRCLK Delay
ASDATA Delay
20
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
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相關(guān)代理商/技術(shù)參數(shù) |
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| EVAL-AD1837EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD1838AEB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
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