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參數(shù)資料
| 型號： | EVAL-AD1837AEB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| 中文描述： | 2的ADC，8 DAC的，96千赫，24位編解碼器 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 523K |
| 代理商： | EVAL-AD1837AEB |
REV. B
–16–
AD1837
FSTDM
INTERNAL
ADC L1
AUX_ADC L2
AUX_ADC L3
AUX_ADC L4
INTERNAL
ADC R1
AUX_ADC R2
AUX_ADC R3
AUX_ADC R4
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
MSB TDM
CH
LEFT
RIGHT
I
2
S—MSB RIGHT
I
2
S—MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
AUX
LRCLK I
2
S
(FROM AUX ADC 1)
AUX
BCLK I
2
S
(FROM AUX ADC 1
)
AAUXDATA1 (IN)
(FROM AUX ADC 1)
AAUXDATA2 (IN)
(FROM AUX ADC 2)
AAUXDATA3 (IN)
(FROM AUX ADC 3)
AUX BCLK FREQUENCY IS 64
FRAME-RATE; TDM BCLK FREQUENCY IS 256
FRAME-RATE.
T
A
2
S
MSB TDM
CH
32
32
MSB TDM
CH
MSB TDM
CH
I
2
S—MSB RIGHT
I
2
S—MSB LEFT
I
2
S—MSB RIGHT
I
2
S—MSB LEFT
INTERNAL
DAC L4
INTERNAL
DAC R4
Figure 11. Aux Mode Timing
Table II. Pin Function Changes in Auxiliary Mode
Pin Name
I
2
S Mode
I
2
S Data Out, Internal ADC
I
2
S Data In, Internal DAC1
I
2
S Data In, Internal DAC2
I
2
S Data In, Internal DAC3
I
2
S Data In, Internal DAC4
LRCLK for ADC
BCLK for ADC
LRCLK In/Out Internal DACs
Aux Mode
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
DSDATA4 (I)/AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
DLRCLK (I)/AUXLRCLK(I/O)
TDM Data Out to SHARC
TDM Data In from SHARC
AUX-I
2
S Data In 1 (from Ext. ADC)
AUX-I
2
S Data In 2 (from Ext. ADC)
AUX-I
2
S Data In 3 (from Ext. ADC)
TDM Frame Sync Out to SHARC (FSTDM)
TDM BCLK Out to SHARC
AUX LRCLK In/Out. Driven by Ext. LRCLK from ADC
in slave mode. In master mode, driven by MCLK/512.
AUX BCLK In/Out. Driven by Ext. BCLK from ADC in
slave mode. In master mode, driven by MCLK/8.
DBCLK (I)/AUXBCLK
(I/O) BCLK In/Out Internal DACs
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| EVAL-AD1839EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
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