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參數資料
| 型號： | EVAL-AD1896EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Automotive Low-Cost Non-Volatile FPGA Family; Voltage: 1.2V; Grade: -5; Package: Lead-Free ftBGA; Pins: 256; Temperature: AUTO; LUTs (k): 8 |
| 中文描述： | AD1896 7.75:1到1:8，192千赫立體聲ASRC評估板 |
| 文件頁數： | 1/28頁 |
| 文件大?。?/td> | 549K |
| 代理商： | EVAL-AD1896EB |
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
EVAL-AD1896EB
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
Analog Devices, Inc., 2001
AD1896 7.75:1 to 1:8, 192 kHz
Stereo ASRC Evaluation Board
OVERVIEW
The AD1896 is a 24-bit, high-performance, single-chip, second
generation Asynchronous Sample Rate Converter (ASRC). The
AD1896 supports sample rates up to 192 kHz with 7.75:1
downsampling and 1:8 upsampling ranges while maintaining
the highest performance. In normal operation, input serial data
(@ input sample rate f
S_IN
) in 3-wire serial format is sourced to
the serial input port pins SCLK_I, LRCLK_I, and SDATA_I.
The output serial data (@ output sample rate f
S
_out) is accessed
via the output serial port pins SCLK_O, LRCLK_O, and
SDATA_O. The LRCLK_I and LRCLK_O signals define the
input and output sample frequency, respectively. The input and
output signals are typically asynchronous with respect to each
other and to the master clock, MCLK_I.
The AD1896 has very flexible serial input and output data ports
for glueless interconnection to audio DACs, DSPs, Digital Inter-
face Receivers (DIR), and Digital Interface Transmitters (DIT).
The AD1896 input and output serial data ports can be config-
ured in left-justified, right-justified (16, 18, 20, and 24 bits),
I
2
S, or TDM mode. Top-level pins are provided for controlling
the data formats and other functional modes of the AD1896
without any serial programming. Other features include bypass
mode, matched phase mode, group delay selection of the digital
filter, mute control, and mute flag pin for an internal error
flagging. Please refer to the AD1896 data sheet for the detailed
product description.
The overall setup of the evaluation board is described briefly
including jumper settings. The AD1896 evaluation board uses a
±
9 V to
±
15 V dc source. Clean regulated 5 V and 3.3 V are
generated to power the AD1896 and other on-board compo-
nents. Separate 5 V supplies are used for analog and digital
sections. Op amps used for the analog filtering are powered
from
±
15 V. Please refer to Appendix A for the block diagram,
schematics, layout plots, Bill of Materials, and PLD code.
INTEGRATED CIRCUIT FUNCTIONS
AD1896 ASRC (U13)
Asynchronous Sample Rate Converter
CS8414 SPDIF Receiver (U1)
Receives the digital signal from an external source in SPDIF/
AES format and recovers the data and clocks. The 3-wire sig-
nals are then sourced to the AD1896 input serial port. SPDIF
receiver supports sample rates up to 96 kHz.
CS8404 SPDIF Transmitter (U6)
Encodes the AD1896 output (3-wire format) in SPDIF format.
SPDIF transmitter supports sample rates up to 96 kHz.
AD1852 Stereo DAC (U12)
Stereo DAC for converting the AD1896 output into stereo analog
outputs. Supports up to 192 kHz sample rates unlike SPDIF
transmitter.
Input CPLD (U2)
This PLD is used to control the input serial port signals of the
AD1896. In addition, it controls SPDIF receiver and other
control signals of the AD1896.
Output CPLD (U3)
This PLD controls the output serial port signals of the AD1896
as well as the SPDIF transmitter and stereo DAC AD1852.
In addition to these components, there is a circuit that divides
the master clock of the AD1896 by two or three, based on the
master/slave clock mode and generates the on-board signals
256 f
S
, EXT256 f
S
, and 128 f
S
(Figure 9 of the AD1896EB
schematic). If the AD1896 output port is operating in 768
×
f
S
master mode, then the master clock is divided by three; and if
the AD1896 output port is operating in 512
×
f
S
master mode,
then the master clock is divided by two. The 256 f
S
clock (for
DAC) is divided by two to generate the 128 f
S
master clock for
SPDIF transmitter.
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