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參數(shù)資料
| 型號(hào)： | EV-ADF4108EB2Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADF4108EB2Z |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
Data Sheet
ADF4108
Rev. E | Page 9 of 20
THEORY OF OPERATION
REFERENCE INPUT STAGE
The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
100k
NC
REFIN NC
NO
SW1
SW2
BUFFER
SW3
TO R COUNTER
POWER-DOWN
CONTROL
0
60
15
-01
6
Figure 10. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 11. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
500
1.6V
500
AGND
RFINA
RFINB
AVDD
BIAS
GENERATOR
0
60
15
-01
7
Figure 11. RF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9, 16/17,
32/33, or 64/65. It is based on a synchronous 4/5 core. A minimum
divide ratio is possible for contiguous output frequencies. This
minimum is determined by P, the prescaler value, and is given
by (P2 P).
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows:
R
f
A
B
P
f
REFIN
VCO
where:
fVCO is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler (8/9, 16/17,
and so on.).
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 6-bit swallow counter
(0 to 63).
fREFIN is the external reference frequency oscillator.
LOAD
FROM RF
INPUT STAGE
PRESCALER
P/P + 1
13-BIT B
COUNTER
TO PFD
6-BIT A
COUNTER
N DIVIDER
MODULUS
CONTROL
N = BP + A
0
6
01
5-
0
18
Figure 12. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
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