AVDD = DV
參數(shù)資料
型號: EV-ADF4108EB2Z
廠商: Analog Devices Inc
文件頁數(shù): 14/20頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADF4108EB2Z
標(biāo)準(zhǔn)包裝: 1
系列: *
Data Sheet
ADF4108
Rev. E | Page 3 of 20
SPECIFICATIONS
AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 k, dBm referred to 50 , TA = TMIN to
TMAX, unless otherwise noted.
Table 1.
Parameter
B Version1
B Chips2
(Typ)
Unit
Test Conditions/Comments
RF CHARACTERISTICS
See Figure 11 for input circuit
RF Input Frequency (RFIN)
1.0/8.0
GHz min/max
For lower frequencies, ensure slew rate (SR) > 320 V/s
RF Input Sensitivity
5/+5
dBm min/max
Maximum Allowable Prescaler
Output Frequency3
300
MHz max
P = 8
325
MHz max
P = 16
REFIN CHARACTERISTICS
REFIN Input Frequency
20/250
MHz min/max
For f < 20 MHz, ensure SR > 50 V/s
REFIN Input Sensitivity4
0.8/VDD
V p-p min/max
Biased at AVDD/25
REFIN Input Capacitance
10
pF max
REFIN Input Current
±100
A max
PHASE DETECTOR
Phase Detector Frequency6
104
MHz max
CHARGE PUMP
Programmable; see Figure 18
ICP Sink/Source
High Value
5
mA typ
With RSET = 5.1 k
Low Value
625
A typ
Absolute Accuracy
2.5
% typ
With RSET = 5.1 k
RSET Range
3.0/11
k typ
ICP Three-State Leakage
1
nA typ
1 nA typical; TA = 25°C
Sink and Source Current Matching
2
% typ
0.5 V ≤ VCP ≤ VP 0.5 V
ICP vs. VCP
1.5
% typ
0.5 V ≤ VCP ≤ VP 0.5 V
ICP vs. Temperature
2
% typ
VCP = VP/2
LOGIC INPUTS
VIH, Input High Voltage
1.4
V min
VIL, Input Low Voltage
0.6
V max
IINH, IINL, Input Current
±1
A max
CIN, Input Capacitance
10
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
1.4
V min
Open-drain output chosen; 1 k pull-up resistor to 1.8 V
VOH, Output High Voltage
VDD 0.4
V min
CMOS output chosen
IOH, Output High Current
100
A max
VOL, Output Low Voltage
0.4
V max
IOL = 500 A
POWER SUPPLIES
AVDD
3.2/3.6
V min/max
DVDD
AVDD
VP
AVDD/5.5
V min/max
AVDD ≤ VP ≤ 5.5 V
IDD (AIDD + DIDD)7
17
mA max
15 mA typ
IP
0.4
mA max
TA = 25°C
Power-Down Mode (AIDD + DIDD)8
10
A typ
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