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參數(shù)資料
| 型號： | ES25P80-75IG2Y |
| 廠商： | 優(yōu)先(蘇州)半導體有限公司 |
| 英文描述： | 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| 中文描述： | 8Mbit的CMOS 3.0伏的閃存與75MHz的SPI總線接口 |
| 文件頁數(shù)： | 6/35頁 |
| 文件大?。?/td> | 450K |
| 代理商： | ES25P80-75IG2Y |
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ESI
6
Rev. 0D May, 11, 2006
ES25P80
Excel Semiconductor inc.
ADVANCED INFORMATION
Polling During a Write, Program, or
Erase Cycle
A further improvement in the time to Write Status
Register (WRSR), Program(PP) or Erase (SE or BE)
can be achieved by not waiting for the worst-case
delay. The Write in Progress (WIP) bit is provided in
the Status Register so that the application program
can monitor its value, polling it to establish when the
previous Write cycle, Program cycle, or Erase cycle
is complete.
Active Power and Standby Power Modes
When Chip Select (CS#) is Low, the device is
enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but
could remain in the Active Power mode until all inter-
nal cycles have completed (Program, Erase, Write
Status Register). The device then goes into the
Standby Power mode. The device consumption
drops to I
SB
. This can be used as an extra Deep
Power Down on mechanism, when the device is not
in active use, to protect the device from inadvertent
Write, Program, or Erase instructions.
Status Register
The Status Register contains a number of status and
control bits, as shown in Figure 7, that can be read
or set (as appropriate) by specific instructions
WIP bit
The Write In Progress (WIP) bit indicates whether
the memory is busy with a Write Status Register,
Program or Erase cycle.
WEL bit
The Write Enable Latch (WEL) bit indicates the sta-
tus of the internal Write Enable Latch.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-vol-
atile. They define the size of the area to be software
protected against Program and Erase instructions.
SRWD bit
The Status Register Write Disable (SRWD) bit is
operated in conjunction with the Write Protect (W#)
signal. The Status Register Write Disable (SRWD)
bit and Write Protect (W#) signal allow the device to
be put in the Hardware Protected mode. In this
mode, the non-volatile bits of the Status Register
(SRWD, BP2, BP1, BP0) become read-only bits.
Hold Condition Modes
The Hold (HOLD#) signal is used to pause any serial
communications with the device without resetting the
clocking sequence. Hold (HOLD#) signal gates the
clock input to the device. However, taking this signal
Low does not terminate any Write Status Register,
Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (CS#) Low. The Hold con-
dition starts on the falling edge of the Hold (HOLD#)
signal, provided that this coincides with Serial Clock
(SCK) being Low (as shown in Figure 3).
The Hold condition ends on the rising edge of the
Hold (HOLD#) signal, provided that this coincides
with Serial Clock (SCK) being Low.
Figure 3. Hold Condition Activation
SCK
HOLD#
Hold Condition
(Standard use)
Hold Condition
(non-standard use)
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