參數(shù)資料
型號(hào): EPM9400
廠商: Altera Corporation
英文描述: Programmable Logic Device Family(MAX9000可編程邏輯系列器件)
中文描述: 可編程邏輯器件系列(MAX9000可編程邏輯系列器件)
文件頁(yè)數(shù): 22/41頁(yè)
文件大?。?/td> 604K
代理商: EPM9400
22
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Figure 11. MAX 9000 JTAG Waveforms
Table 10
shows the JTAG timing parameters and values for MAX 9000
devices.
f
For detailed information on JTAG operation in MAX 9000 devices, refer to
Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera
Devices)
.
Table 10. JTAG Timing Parameters & Values for MAX 9000 Devices
Symbol
Parameter
Min
Max
Unit
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
TCK
clock period
TCK
clock high time
TCK
clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
100
50
50
20
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
25
25
20
45
25
25
25
TDO
TCK
t
JPZX
t
JPCO
t
JPH
t
JPXZ
t
JCP
t
JPSU
t
JCL
t
JCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
t
JSSU
t
JSH
t
JSCO
t
JSXZ
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