參數(shù)資料
型號： EPM7064BFC100-7
廠商： ALTERA CORP
元件分類： PLD
英文描述： EE PLD, 3.5 ns, PBGA100
封裝： FBGA-100
文件頁數(shù)： 7/66頁
文件大?。?/td> 962K
代理商： EPM7064BFC100-7
Altera Corporation
15
MAX 7000B Programmable Logic Device Data Sheet
In-System
Programma-
bility (ISP)
MAX 7000B devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient
iterations during design development and debugging cycles. The
MAX 7000B architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 2.5-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 k.
MAX 7000B devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a PCB with standard pick-and-place equipment before they are
programmed. MAX 7000B devices can be programmed by downloading
the information via in-circuit testers, embedded processors, the Altera
MasterBlaster communications cable, and the ByteBlasterMV parallel port
download cable. Programming the devices after they are placed on the
board eliminates lead damage on high-pin-count packages (e.g., QFP
packages) due to device handling. MAX 7000B devices can be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. A constant algorithm uses a
pre-defined (non-adaptive) programming sequence that does not take
advantage of adaptive algorithm programming time improvements.
Some in-circuit testers cannot program using an adaptive algorithm.
Therefore, a constant algorithm must be used. MAX 7000B devices can be
programmed with either an adaptive or constant (non-adaptive)
algorithm.
The Jam Standard Test and Programming Language (STAPL), JEDEC
standard JESD-71, can be used to program MAX 7000B devices with
in-circuit testers, PCs, or embedded processors.
f For more information on using the Jam language, see Application Note 88
(Using the Jam Language for ISP & ICR via an Embedded Processor) and
Application Note 122 (Using STAPL for ISP & ICR via an Embedded Processor).
The ISP circuitry in MAX 7000B devices is compliant with the IEEE
Std. 1532 specification. The IEEE Std. 1532 is a standard developed to
allow concurrent ISP between multiple PLD vendors.
相關(guān)PDF資料
PDF描述
EPM7064BTC100-3 EE PLD, 3.5 ns, PQFP100
EPM7064BTC100-5 EE PLD, 3.5 ns, PQFP100
EPM7064BTC100-7 EE PLD, 3.5 ns, PQFP100
EPM7064BTC44-3 EE PLD, 3.5 ns, PQFP44
EPM7064BTC44-5 EE PLD, 3.5 ns, PQFP44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7064BLC44-3 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPM7064BLC44-5 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPM7064BLC44-7 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPM7064BTC100-3 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064BTC100-3N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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