參數(shù)資料
型號(hào): EPM7064BFC100-7
廠商: ALTERA CORP
元件分類: PLD
英文描述: EE PLD, 3.5 ns, PBGA100
封裝: FBGA-100
文件頁(yè)數(shù): 48/66頁(yè)
文件大小: 962K
代理商: EPM7064BFC100-7
52
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Table 31. EPM7512B Internal Timing Parameters
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-7
-10
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
0.3
0.5
ns
tIO
I/O input pad and buffer delay
0.3
0.5
ns
tFIN
Fast input delay
2.2
3.2
4.0
ns
tFIND
Programmable delay adder for
fast input
1.5
ns
tSEXP
Shared expander delay
1.5
2.1
2.7
ns
tPEXP
Parallel expander delay
0.4
0.5
0.7
ns
tLAD
Logic array delay
1.7
2.3
3.0
ns
tLAC
Logic control array delay
1.5
2.0
2.6
ns
tIOE
Internal output enable delay
0.1
0.2
ns
tOD1
Output buffer and pad delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
0.9
1.2
1.6
ns
tOD3
Output buffer and pad delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
5.9
6.2
6.6
ns
tZX1
Output buffer enable delay
slow slew rate = off
VCCIO = 3.3 V
C1 = 35 pF
2.8
3.8
5.0
ns
tZX3
Output buffer enable delay
slow slew rate = on
VCCIO = 2.5 V or 3.3 V
C1 = 35 pF
7.8
8.8
10.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
2.8
3.8
5.0
ns
tSU
Register setup time
1.5
2.0
2.6
ns
tH
Register hold time
0.4
0.5
0.7
ns
tFSU
Register setup time of fast input
0.8
1.1
ns
tFH
Register hold time of fast input
1.2
1.4
ns
tRD
Register delay
0.5
0.7
1.0
ns
tCOMB
Combinatorial delay
0.2
0.3
0.4
ns
tIC
Array clock delay
1.8
2.4
3.1
ns
tEN
Register enable time
1.5
2.0
2.6
ns
tGLOB
Global control delay
2.0
2.8
3.6
ns
tPRE
Register preset time
1.0
1.4
1.9
ns
tCLR
Register clear time
1.0
1.4
1.9
ns
tPIA
PIA delay
2.4
3.4
4.5
ns
tLPA
Low-power adder
2.0
2.7
3.6
ns
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