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參數(shù)資料
| 型號： | EPM7064AELC44-5 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | EE PLD, 5 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 7/51頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | EPM7064AELC44-5 |
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Altera Corporation
609
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
In-System
Programma-
bility (ISP)
MAX 7000A devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1-1990 (JTAG) interface. ISP offers quick,
efficient iterations during design development and debugging cycles. The
MAX 7000A architecture internally generates the high programming
voltages required to program EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 k
.
MAX 7000AE devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that provides safe
operation when in-system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed. This feature is available in EPM7032AE,
EPM7064AE, EPM7128AE, EPM7256AE, and EPM7512AE devices only.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick-and-place equipment
before they are programmed. MAX 7000A devices can be programmed by
downloading the information via in-circuit testers, embedded processors,
the Altera BitBlaster serial download cable, and the ByteBlasterMV
parallel port download cable. Programming the devices after they are
placed on the board eliminates lead damage on high-pin-count packages
(e.g., QFP packages) due to device handling. MAX 7000A devices can be
reprogrammed after a system has already shipped to the field. For
example, product upgrades can be performed in the field via software or
modem.
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
cannot support an adaptive algorithm, Altera offers devices tested with a
constant algorithm. Devices tested to the constant algorithm contain an
“F” suffix in the ordering code and are marked with an “F” on the bottom
right-hand corner of the device.
The Jam programming and test language can be used to program
MAX 7000A devices with in-circuit testers, PCs, or embedded processors.
f For more information on using the Jam language, see Application Note 88
(Using the Jam Language for ISP & ICR via an Embedded Processor).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPM7064AELI44-5 | EE PLD, 5 ns, PQCC44 |
| EPM7128AELC84-6 | EE PLD, 6 ns, PQCC84 |
| EPM7128AELI84-6 | EE PLD, 6 ns, PQCC84 |
| EPM7064AETC100-5 | EE PLD, 5 ns, PQFP100 |
| EPM7064AETC100-6 | EE PLD, 6 ns, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7064AELC44-7 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 36 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7064AELC84-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| EPM7064AELC84-4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| EPM7064AELC84-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| EPM7064AELC84-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
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