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| 型號： | EPM7032TC44-10 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可編程邏輯器件系列 |
| 文件頁數(shù)： | 50/60頁 |
| 文件大?。?/td> | 943K |
| 代理商： | EPM7032TC44-10 |
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50
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in
Table 11 on page 24
. See
Figure 12
for more information on switching waveforms.
(2)
These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(3)
This minimum pulse width for preset and clear applies for both global clear and array controls. The
t
LPA
parameter
must be added to this minimum width if the clear or reset signal incorporates the
t
LAD
parameter into the signal
path.
(4)
This parameter is measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(5)
Operating conditions: V
CCIO
= 2.5
±
0.2 V for commercial and industrial use.
(6)
The
t
LPA
parameter must be added to the
t
LAD
,
t
LAC
,
t
IC
,
t
EN
,
t
SEXP
,
t
ACL
, and
t
CPPW
parameters for macrocells
running in low-power mode.
Power
Consumption
Supply power (P) versus frequency (
f
MAX
, in MHz) for MAX 7000A
devices is calculated with the following equation:
P = P
INT
+ P
IO
= I
CCINT
×
V
CC
+ P
IO
The P
IO
value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices)
.
The I
CCINT
value depends on the switching frequency and the application
logic. The I
CCINT
value is calculated with the following equation:
I
CCINT
=
(A
×
MC
TON
) + [B
×
(MC
DEV
– MC
TON
)] + (C
×
MC
USED
×
f
MAX
×
tog
LC
)
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
t
CLR
t
PIA
t
LPA
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
1.6
1.6
2.7
2.5
1.1
2.3
2.3
1.3
11.0
2.0
2.0
3.4
3.1
1.4
2.9
2.9
1.6
10.0
2.7
2.7
4.5
4.2
1.8
3.8
3.8
2.1
10.0
3.2
3.2
5.4
5.0
2.2
4.6
4.6
2.6
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
(6)
Table 27. EPM7256A Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-6
-7
-10
-12
Min
Max
Min
Max
Min
Max
Min
Max
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7032TC44-12 | 制造商:Altera Corporation 功能描述:IC MAX 44TQFP 制造商:Altera Corporation 功能描述:IC CPLD 32MC 12NS 44TQFP |
| EPM7032TC4415 | 制造商:ALTERA 功能描述:* |
| EPM7032TC44-15 | 功能描述:IC MAX 7000 CPLD 32 44-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:MAX® 7000 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| EPM7032TC44-6 | 制造商:Altera Corporation 功能描述:IC MAX 44TQFP 制造商:Altera Corporation 功能描述:IC CPLD 32MC 6NS 44TQFP |
| EPM7032TC44-7 | 制造商:Altera Corporation 功能描述:IC MAX 44TQFP 制造商:Altera Corporation 功能描述:IC CPLD 32MC 7.5NS 44TQFP |
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