參數(shù)資料
型號(hào): EPM7032TC44-10
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 33/60頁
文件大?。?/td> 943K
代理商: EPM7032TC44-10
Altera Corporation
33
MAX 7000A Programmable Logic Device Data Sheet
Table 16. EPM7064AE External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-4
-7
-10
Min
Max
Min
Max
Min
Max
t
PD1
Input to non-
registered output
I/O input to non-
registered output
Global clock setup
time
Global clock hold time
(2)
Global clock setup
time of fast input
Global clock hold time
of fast input
Global clock to output
delay
Global clock high time
Global clock low time
Array clock setup time
(2)
Array clock hold time
Array clock to output
delay
Array clock high time
Array clock low time
Minimum pulse width
for clear and preset
Minimum global clock
period
Maximum internal
global clock frequency
Minimum array clock
period
Maximum internal
array clock frequency
C1 = 35 pF
(2)
C1 = 35 pF
(2)
(2)
4.5
7.5
10.0
ns
t
PD2
4.5
7.5
10.0
ns
t
SU
2.8
4.7
6.2
ns
t
H
t
FSU
0.0
2.5
0.0
3.0
0.0
3.0
ns
ns
t
FH
0.0
0.0
0.0
ns
t
CO1
C1 = 35 pF
1.0
3.1
1.0
5.1
1.0
7.0
ns
t
CH
t
CL
t
ASU
t
AH
t
ACO1
2.0
2.0
1.6
0.3
1.0
3.0
3.0
2.6
0.4
1.0
4.0
4.0
3.6
0.6
1.0
ns
ns
ns
ns
ns
(2)
C1 = 35 pF
(2)
4.3
7.2
9.6
t
ACH
t
ACL
t
CPPW
2.0
2.0
2.0
3.0
3.0
3.0
4.0
4.0
4.0
ns
ns
ns
(3)
t
CNT
(2)
4.5
7.4
10.0
ns
f
CNT
(2)
,
(4)
222.2
135.1
100.0
MHz
t
ACNT
(2)
4.5
7.4
10.0
ns
f
ACNT
(2)
,
(4)
222.2
135.1
100.0
MHz
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