參數(shù)資料
型號: EPM7032TC44-10
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 30/60頁
文件大?。?/td> 943K
代理商: EPM7032TC44-10
30
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
Tables 14
through
27
show EPM7032AE, EPM7064AE, EPM7128AE,
EPM7256AE, EPM7512AE, EPM7128A, and EPM7256A timing
information.
Table 14. EPM7032AE External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-4
-7
-10
Min
Max
Min
Max
Min
Max
t
PD1
Input to non-registered
output
I/O input to non-registered
output
Global clock setup time
Global clock hold time
Global clock setup time of
fast input
Global clock hold time of
fast input
Global clock to output delay C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock period
(2)
Maximum internal array
clock frequency
C1 = 35 pF
(2)
4.5
7.5
10
ns
t
PD2
C1 = 35 pF
(2)
4.5
7.5
10
ns
t
SU
t
H
t
FSU
(2)
(2)
2.9
0.0
2.5
4.7
0.0
3.0
6.3
0.0
3.0
ns
ns
ns
t
FH
0.0
0.0
0.0
ns
t
CO1
t
CH
t
CL
t
ASU
t
AH
t
ACO1
t
ACH
t
ACL
t
CPPW
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
2.0
3.0
1.0
3.0
3.0
2.5
0.5
1.0
3.0
3.0
3.0
5.0
1.0
4.0
4.0
3.6
0.5
1.0
4.0
4.0
4.0
6.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
(2)
C1 = 35 pF
(2)
4.3
7.2
9.4
(3)
t
CNT
(2)
4.4
7.2
9.7
ns
f
CNT
(2)
,
(4)
227.3
138.9
103.1
MHz
t
ACNT
f
ACNT
4.4
7.2
9.7
ns
MHz
(2)
,
(4)
227.3
138.9
103.1
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EPM7032 Programmable Logic Device Family
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