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參數(shù)資料
| 型號(hào)： | EPM570 |
| 廠商： | Altera Corporation |
| 英文描述： | JTAG & In-System Programmability |
| 中文描述： | JTAG接口 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 103K |
| 代理商： | EPM570 |
Altera Corporation
June 2004
Core Version a.b.c variable
3–5
MAX II Device Handbook, Volume 1
JTAG & In-System Programmability
debugging cycles. The logic, circuitry, and interconnects in the MAX II
architecture are configured with flash-based SRAM configuration
elements. These SRAM elements require configuration data to be loaded
each time the device is powered. The process of loading the SRAM data
is called configuration. The on-chip configuration flash memory (CFM)
block stores the SRAM element’s configuration data. The CFM block
stores the design’s configuration pattern in a reprogrammable flash array.
During ISP, the MAX II JTAG and ISP circuitry programs the design
pattern into the CFM block’s non-volatile flash array.
The MAX II JTAG and ISP controller internally generate the high
programming voltages required to program the CFM cells, allowing in-
system programming with any of the recommended operating external
voltage supplies (i.e., 3.3 V/2.5 V or 1.8 V for the MAX II devices with a
“G” ordering code). ISP can be performed anytime after V
CCINT
and all
V
CCIO
banks have been fully powered and the device has completed the
configuration power-up time. By default, during in-system
programming, the I/O pins are tri-stated and weakly pulled-up to V
CCIO
to eliminate board conflicts. The pull-up value ranges from 5 to 40 k
.
There are two other options in MAX II devices that allow user control of
I/O state or behavior during ISP.
f
For more information, refer to
“In-System Programming Clamp” on
page 3–8
and
“Real-Time ISP” on page 3–8
.
These devices also offer an
ISP_DONE
bit that provides safe operation
when in-system programming is interrupted. This
ISP_DONE
bit, which
is the last bit programmed, prevents all I/O pins from driving until the
bit is programmed.
IEEE 1532 Support
The JTAG circuitry and ISP instruction set in MAX II devices is compliant
to the IEEE 1532-2002 programming specification. This provides
industry-standard hardware and software for in-system programming
among multiple vendor programmable logic devices (PLDs) in a JTAG
chain.
The MAX II 1532 BSDL files will be released on the Altera web site when
available.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM570100C5N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:The MAX II family of instant-on, non-volatile CPLDs is based on a 0.18-m, |
| EPM570F100A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM570F100A5N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 440 Macro 76 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM570F100C | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:MAX II Device Family |
| EPM570F100C4N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX II 440 Macro 76 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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