參數(shù)資料
型號(hào)： EPF8282AV
廠商： Altera Corporation
英文描述： IRDA ENCODE/DECODE
中文描述： 系列可編程邏輯元件
文件頁(yè)數(shù)： 15/61頁(yè)
文件大小： 979K
代理商： EPF8282AV
Altera Corporation
15
FLEX 8000 Programmable Logic Device Family Data Sheet
Asynchronous Clear
A register is cleared by one of the two
LABCTRL
signals. When the
CLRn
port receives a low signal, the register is set to zero.
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load
or an asynchronous clear. If
DATA3
is tied to
VCC
, asserting
LABCTRLl
asynchronously loads a
1
into the register. Alternatively, the
MAX+PLUS II software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two
LABCTRL
signals, the
DATA3
input is not
needed and can be used for one of the LE operating modes.
Asynchronous Clear & Preset
When implementing asynchronous clear and preset,
LABCTRL1
controls
the preset and
LABCTRL2
controls the clear. The
DATA3
input is tied to
VCC
;
therefore, asserting
LABCTRL1
asynchronously loads a
1
into the register,
effectively presetting the register. Asserting
LABCTRL2
clears the register.
Asynchronous Load with Clear
When implementing an asynchronous load with the clear,
LABCTRL1
implements the asynchronous load of
DATA3
by controlling the register
preset and clear.
LABCTRL2
implements the clear by controlling the
register clear.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with a preset,
the MAX+PLUS II software provides preset control by using the clear and
inverting the input and output of the register. Asserting
LABCTRL2
clears
the register, while asserting
LABCTRL1
loads the register. The
MAX+PLUS II software inverts the signal that drives the
DATA3
signal to
account for the inversion of the register’s output.
Asynchronous Load without Clear or Preset
When implementing an asynchronous load without the clear or preset,
LABCTRL1
implements the asynchronous load of
DATA3
by controlling the
register preset and clear.
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