參數(shù)資料
型號： EPF6016ATI100-2
廠商： Altera
文件頁數(shù)： 16/52頁
文件大小： 0K
描述： IC FLEX 6000 FPGA 16K 100-TQFP
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 270
系列： FLEX 6000
LAB/CLB數(shù)： 132
邏輯元件/單元數(shù)： 1320
輸入/輸出數(shù)： 81
門數(shù)： 16000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 100-TQFP
供應商設備封裝： 100-TQFP（14x14）
Altera Corporation
23
FLEX 6000 Programmable Logic Device Family Data Sheet
I/O Elements
An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can
be used as input, output, or bidirectional pins. An IOE receives its data
signals from the adjacent local interconnect, which can be driven by a row
or column interconnect (allowing any LE in the device to drive the IOE) or
by an adjacent LE (allowing fast clock-to-output delays). A FastFLEXTM
I/O pin is a row or column output pin that receives its data signals from
the adjacent local interconnect driven by an adjacent LE. The IOE receives
its output enable signal through the same path, allowing individual
output enables for every pin and permitting emulation of open-drain
buffers. The Altera Compiler uses programmable inversion to invert the
data or output enable signals automatically where appropriate. Open-
drain emulation is provided by driving the data input low and toggling
the OE of each IOE. This emulation is possible because there is one OE per
pin.
A chip-wide output enable feature allows the designer to disable all pins
of the device by asserting one pin (DEV_OE). This feature is useful during
board debugging or testing.
Figure 12 shows the IOE block diagram.
Figure 12. IOE Block Diagram
From LAB Local Interconnect
Slew-Rate
Control
From LAB Local Interconnect
To Row or Column Interconnect
Chip-Wide Output Enable
Delay
相關PDF資料
PDF描述
A3P600-2FG144 IC FPGA 1KB FLASH 600K 144-FBGA
ASM22DTAH CONN EDGECARD 44POS R/A .156 SLD
ASM22DTAD CONN EDGECARD 44POS R/A .156 SLD
A3P600-2FGG144 IC FPGA 1KB FLASH 600K 144-FBGA
M1A3P600-2FG144 IC FPGA 1KB FLASH 600K 144-FBGA
相關代理商/技術參數(shù)
參數(shù)描述
EPF6016ATI100-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 132 LABs 81 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6016ATI144-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPF6016ATI144-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 132 LABs 117 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6016ATI144-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 132 LABs 117 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF6016BC256-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 6000 132 LABs 204 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*