參數(shù)資料
型號(hào)： EPC1064
廠商： Electronic Theatre Controls, Inc.
英文描述： Configuration Devices for SRAM-Based LUT Devices
中文描述： 配置SRAM器件基于LUT的器件
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 380K
代理商： EPC1064
Altera Corporation
9
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Table 4. EPC2, EPC1, & EPC1441 Pin Functions During ACEX 1K, APEX 20K, FLEX 10K, FLEX 6000 &
Mercury Configuration (Part 1 of 2)
Pin Name
Pin Number
Pin
Type
Description
8-Pin
PDIP
(1)
20-Pin
PLCC
32-Pin
TQFP
(2)
DATA
1
2
31
Output
Serial data output. The
DATA
pin is tri-stated before
configuration when the
nCS
pin is high, and after the
configuration device finishes sending its configuration
data. This operation is independent of the device
’
s
position in the cascade chain.
DCLK
is a clock output when configuring with a single
configuration device or when the configuration device is
the first device in a configuration device chain.
DCLK
is
a clock input for subsequent configuration devices in a
configuration device chain. Rising edges on
DCLK
increment the internal address counter and present the
next bit of data to the
DATA
pin. The counter is
incremented only if the
OE
input is held high, the
nCS
input is held low, and all configuration data has not
been transferred to the target device. When configuring
with the first EPC2 or EPC1 device in a configuration
device chain or with a single EPC1441 device, the
DCLK
pin drives low after configuration is complete or
when
OE
is low.
Output enable (active high) and reset (active low). A
low logic level resets the address counter. A high logic
level enables
DATA
and permits the address counter to
count. If this pin is low (reset) during configuration, the
internal oscillator becomes inactive and
DCLK
drives
low. See
“
Error Detection Circuitry
”
on
page 17
.
Chip select input (active low). A low input allows
DCLK
to increment the address counter and enables
DATA
to
drive out. If the EPC1 or EPC2 is reset with
nCS
low, the
device initializes as the first device in a configuration
chain. If the EPC1 or EPC2 device is reset with
nCS
high, the device initializes as the subsequent device in
the chain.
Cascade select output (active low). This output goes
low when the address counter has reached its
maximum value. In a chain of EPC1 or EPC2 devices,
the
nCASC
pin of one device is connected to the
nCS
pin
of the next device, which permits
DCLK
to clock data
from the next EPC1 or EPC2 device in the chain.
DCLK
2
4
2
I/O
OE
(3)
3
8
7
Open-
Drain
I/O
nCS
(3)
4
9
10
Input
nCASC
(4)
6
12
15
Output
相關(guān)PDF資料
PDF描述
EPC1064V Configuration Devices for SRAM-Based LUT Devices
EPC1213 Configuration Devices for SRAM-Based LUT Devices
EPC1441 Configuration Devices for SRAM-Based LUT Devices
EPC1064 Configuration Devices for ACEX, APEX, FLEX & Mercury Devices
EPC1064V Configuration Devices for ACEX, APEX, FLEX & Mercury Devices
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