Note: The effect of branches should also be accounted for, as it is the instruction stream as seen by the coprocessor that matters," />
參數(shù)資料
型號(hào): EP9315-IB
廠商: Cirrus Logic Inc
文件頁數(shù): 3/16頁
文件大?。?/td> 0K
描述: IC ARM920T MCU 200MHZ 352-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: EP9
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 200MHz
連通性: EBI/EMI,EIDE,以太網(wǎng),I²C,IrDA,鍵盤/觸摸屏,PCMCIA,SPI,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,LCD,LED,MaverickKey,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 352-BGA
包裝: 托盤
配用: 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9
其它名稱: 598-1262
ER638E2B
11
Note: The effect of branches should also be accounted for, as it is the instruction stream as seen by the
coprocessor that matters, not the order of instructions in the source code. To avoid this error when entering
exception and interrupt handlers, the first seven instruction in an interrupt or exception handler should not
be a coprocessor instructions.
Description 5
When operating in serialized mode2, cfrshl32 and cfrshl64 do not work properly. The instructions shift by an
unpredictable amount, but cause no other side effects.
Workaround
One workaround is to avoid these instructions. With this approach, an alternative instruction sequence may
accomplish the shift with the following steps:
- Move the data to be shifted to ARM register(s)
- Shift the data using non-coprocessor instructions
- Move the shifted data back to the coprocessor.
Another workaround is to never operate in serialized mode. With this approach, synchronous exceptions are
not possible.
Description 6
If an interrupt occurs during the execution of cfldr32 or cfmv64lr, the instruction may not sign extend the
result correctly.
Either instruction places a 32 bit value into the lower half of one of the coprocessor general purpose registers
c0 through c15 and sign extends the high (32nd) bit through the upper half of the register. If an IRQ or FIQ
to the ARM processor interrupts either of these instructions at the right time, the coprocessor will properly
load the low 32 bits of the target register, but instead of sign extending it will replicate the low 32 bit into the
upper 32 bits. Code that depends on sign extension will fail to operate correctly.
Workaround
Possible workarounds include:
- Disable interrupts when executing cfldr32 or cfmv64lr instructions.
- Avoid executing these two instructions.
- Do not depend on the sign extension to occur; that is, ignore the upper word in any calculations
involving data loaded using these instructions.
- Add extra code to sign extend the lower word after it is loaded by explicitly forcing the upper word
to be all zeroes or all ones, as appropriate. It is possible to do this selectively in exception or interrupt
handler code. If the instruction preceding the interrupted instruction can be determined, and it is a
cfldr32 or cfmv64lr, the instruction may be re-executed or explicitly sign extended before returning
from interrupt or exception.
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