參數(shù)資料
型號: EP9312-CB
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: Universal Platform System-on-chip Processor
中文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝: 27 X 27 MM, PLASTIC, BGA-352
文件頁數(shù): 33/62頁
文件大?。?/td> 884K
代理商: EP9312-CB
DS515PP7
Copyright 2005 Cirrus Logic (All Rights Reserved)
33
EP9312
Universal Platform SOC Processor
Note:
1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (15:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is
to be extended is made by the host after t
A
from the assertion of DIORn or DIOWn. The assertion and negation or IORDY
are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before t
A
, but causes IORDY to be asserted before t
A
. IORDY is released prior to negation
and may be asserted for no more than t
C
before release: no wait generated.
3-3 Device negates IORDY before t
A
. IORDY is released prior to negation and may be asserted for no more than t
C
before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (15:0) for t
RD
before asserting IORDY.
Figure 18. PIO Data Transfer to/from Device
ADDR valid
(Note 1)
DIORn/
DIOWn
WRITE
DD(15:0)
(Note 2)
READ
DD(15:0)
(Note 2)
IORDY
(Note 3,3-1)
IORDY
(Note 3,3-2)
IORDY
(Note 3,3-3)
t
0
t
1
t
2
t
9
t
2i
t
3
t
4
t
5
t
6
t
6z
t
A
t
B
t
C
t
C
t
RD
t
DDV
相關PDF資料
PDF描述
EP9312-CBZ Universal Platform System-on-chip Processor
EP9312-EB Universal Platform System-on-chip Processor
EP9312-EBZ Universal Platform System-on-chip Processor
EP9312-IB Universal Platform System-on-chip Processor
EP9312-IBZ Universal Platform System-on-chip Processor
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