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參數(shù)資料
| 型號： | EP9312-CB |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Universal Platform System-on-chip Processor |
| 中文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-352 |
| 文件頁數(shù)： | 30/62頁 |
| 文件大?。?/td> | 884K |
| 代理商： | EP9312-CB |
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Copyright 2005 Cirrus Logic (All Rights Reserved)
DS515PP7
EP9312
Universal Platform SOC Processor
IDE Interface
Register Transfers
Note:
1. t
0
is the minimum total cycle time, t
2
is the minimum DIORn / DIOWn assertion time, and t
2i
is the minimum DIORn / DIOWn
negation time. A host implementation shall lengthen t
2
and/or t
2i
to ensure that t
0
is equal to or greater than the value
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.
3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host
shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the t
A
after the activation of DIORn or DIOWn, then t
5
shall be met and t
RD
is not applicable. If the device is driving IORDY
negated at the time t
A
after the activation of DIORn or DIOWn, then t
RD
shall be met and t
5
is not applicable.
4. Timings based upon software control. See User’s Guide.
5. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t
0
by utilizing the
16-bit PIO value.
6. All IDE timing is based upon HCLK = 100 MHz.
Parameter
Symbol
Mode 0
(in ns)
Mode 1
(in ns)
Mode 2
(in ns)
Mode 3
(in ns)
Mode 4
(in ns)
Cycle time
(min)
(Notes 1, 4, 5)
t
0
600
383
330
180
120
Address valid to DIORn / DIOWn setup
(min)
(Note 4)
t
1
70
50
30
30
25
DIORn / DIOWn pulse width 8-bit
(min)
(Note 1, 4)
t
2
290
290
290
80
70
DIORn / DIOWn recovery time
(min)
(Note 1, 4)
t
2i
-
-
-
70
25
DIOWn data setup
(min)
(Note 4)
t
3
60
45
30
30
20
DIOWn data hold
(min)
t
4
0
0
0
0
0
DIORn data setup
(min)
t
5
20
20
20
20
20
DIORn data hold
(min)
t
6
0
0
0
0
0
DIORn data high impedance state
(max)
(Note 2, 4)
t
6z
30
30
30
30
30
DIORn / DIOWn to address valid hold
(min)
(Note 4)
t
9
20
15
10
10
10
Read Data Valid to IORDY
active (if IORDY initially low after t
A
)
(min)
(Note 4)
t
RD
0
0
0
0
0
IORDY Setup time
(Note 3, 4)
t
A
35
35
35
35
35
IORDY Pulse Width
(max)
(Note 4)
t
B
1250
1250
1250
1250
1250
IORDY assertion to release
(max)
t
C
5
5
5
5
5
DIOWn assert to data valid
(max)
t
DDV
10
10
10
10
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP9312-CBZ | Universal Platform System-on-chip Processor |
| EP9312-EB | Universal Platform System-on-chip Processor |
| EP9312-EBZ | Universal Platform System-on-chip Processor |
| EP9312-IB | Universal Platform System-on-chip Processor |
| EP9312-IBZ | Universal Platform System-on-chip Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP9312-CB/E1 | 制造商:Cirrus Logic 功能描述: |
| EP9312-CB/E2 | 制造商:Cirrus Logic 功能描述: |
| EP9312-CBREVD1 | 制造商:Cirrus Logic 功能描述: |
| EP9312-CBREVE0 | 制造商:Cirrus Logic 功能描述: |
| EP9312-CBREVE1 | 制造商:Cirrus Logic 功能描述: |
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