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參數(shù)資料
| 型號： | EP9302-IQZ |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | High-speed ARM9 System-on-chip Processor with MaverickCrunch |
| 中文描述： | 高速ARM9的系統(tǒng)級芯片處理器MaverickCrunch |
| 文件頁數(shù)： | 10/42頁 |
| 文件大?。?/td> | 302K |
| 代理商： | EP9302-IQZ |
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Copyright 2005 Cirrus Logic (All Rights Reserved)
DS653PP3
EP9302
High-speed ARM9 System-on-chip Processor with MaverickCrunch
Reset and Power Management
The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.
Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.
The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).
Hardware Debug Interface
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
12-Channel DMA Controller
The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
The request bus is a collection of requests, Serial Audio
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
Internal Boot ROM
The Internal 16-kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP9301 User’s Guide
for operational details.
Table N. Reset and Power Management Pin Assignments
Pin Mnemonic
Pin Name - Description
PRSTn
Power On Reset
RSTOn
User Reset In/Out – Open Drain –
Preserves Real Time Clock value
Table O. Hardware Debug Interface
Pin Mnemonic
Pin Name - Description
TCK
JTAG Clock
TDI
JTAG Data In
TDO
JTAG Data Out
TMS
JTAG Test Mode Select
TRSTn
JTAG Port Reset
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