參數(shù)資料
型號(hào)： EP7312-CV-90
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
中文描述： 32-BIT, FLASH, 90 MHz, RISC MICROCONTROLLER, PQFP208
封裝： LQFP-208
文件頁(yè)數(shù)： 54/64頁(yè)
文件大?。?/td> 1710K
代理商： EP7312-CV-90
54
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
DS508PP5
EP7312
High-Performance, Low-Power System on Chip
*
“
With p/u
”
means with internal pull-up of 100 KOhms on the pin.
Strength 1 = 4 ma
Strength 2 = 12 ma
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
JTAG Boundary Scan Signal Ordering
R5
SSITXDA
1
Low
O
DAI/CODEC/SSI2 serial data output
R6
nADCCS
1
High
O
SSI1 ADC chip select
R7
VDDIO
Pad power
Digital I/O power, 3.3V
R8
ADCOUT
1
Low
O
SSI1 ADC serial data output
R9
COL[7]
1
High
O
Keyboard scanner column drive
R10
COL[3]
1
High
O
Keyboard scanner column drive
R11
COL[1]
1
High
O
Keyboard scanner column drive
R12
D[30]
1
Low
I/O
Data I/O
R13
A[27]/DRA[0]
2
Low
O
System byte address / SDRAM address
R14
A[25]/DRA[2]
2
Low
O
System byte address / SDRAM address
R15
VDDIO
Pad power
Digital I/O power, 3.3V
R16
A[24]/DRA[3]
1
Low
O
System byte address / SDRAM address
T1
VDDRTC
RTC power
Real time clock power, 2.5V
T2
PD[7]/SDQM[1]
1
Low
I/O
GPIO port D / SDRAM byte lane mask
T3
PD[6]/SDQM[0]
1
Low
I/O
GPIO port D / SDRAM byte lane mask
T4
PD[3]
1
Low
I/O
GPIO port D
T5
SSICLK
1
Input
I/O
DAI/CODEC/SSI2 serial clock
T6
SSIRXFR
1
Input
I/O
DAI/CODEC/SSI2 frame sync
T7
VDDCORE
Core power
Core power, 2.5V
T8
DRIVE[0]
2
High /
Low
I/O
PWM drive output
T9
FB[1]
I
PWM feedback input
T10
COL[5]
1
High
O
Keyboard scanner column drive
T11
VDDIO
Pad power
Digital I/O power, 3.3V
T12
BUZ
1
Low
O
Buzzer drive output
T13
D[28]
1
Low
I/O
Data I/O
T14
A[26]/DRA[1]
2
Low
O
System byte address / SDRAM address
T15
D[25]
1
Low
I/O
Data I/O
T16
VSSIO
Pad ground
I/O ground
Table 23. JTAG Boundary Scan Signal Ordering
LQFP
Pin No.
TFBGA
Ball
PBGA
Ball
Signal
Type
Position
1
B3
B1
nCS[5]
O
1
4
A2
C2
EXPCLK
I/O
3
5
B1
E4
WORD
O
6
6
E3
D1
WRITE/nSDRAS
O
8
7
C1
F5
RUN/CLKEN
O
10
Table 22. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
Description
相關(guān)PDF資料
PDF描述
EP7312-CV-C HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
EP7312-EB-90 HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7312-CV-C 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
EP7312-CVZ 功能描述:音頻片上系統(tǒng) - SoC IC Hgh-Prfrmnc Low- Power SOC w/SDRAM RoHS:否 制造商:Cirrus Logic
EP7312-CVZ-90 功能描述:音頻片上系統(tǒng) - SoC IC Hgh-Prfrmnc Low- Power SOC w/SDRAM RoHS:否 制造商:Cirrus Logic
EP7312-CVZR 功能描述:音頻片上系統(tǒng) - SoC IC Hgh-Prfrmnc Low- Power SOC w/SDRAM RoHS:否 制造商:Cirrus Logic
EP7312-EB-90 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE
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