- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362742 > EP7312-CV-90 (CIRRUS LOGIC INC) HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE PDF資料下載
參數(shù)資料
| 型號： | EP7312-CV-90 |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| 中文描述： | 32-BIT, FLASH, 90 MHz, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | LQFP-208 |
| 文件頁數(shù)： | 25/64頁 |
| 文件大?。?/td> | 1710K |
| 代理商： | EP7312-CV-90 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
DS508PP5
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
25
EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
EXPCLK
nCS
A
nMOE
HALF
WORD
WORD
D
nMWE
EXPRDY
WRITE
t
CSd
t
Ad
t
MWd
t
MWh
t
MWd
t
MWd
t
MWd
t
MWh
t
MWh
t
MWh
t
Ah
t
Ah
t
Ah
t
EXs
t
EXh
t
CSh
t
Dv
t
Dv
t
Dv
t
Dnv
t
Dnv
t
Dnv
t
Dv
t
HWd
t
WDd
Figure 10. Static Memory Burst Write Cycle Timing Measurement
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7312-CV-C | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7312-EB-90 | HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7312-EB-C | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7312-ER-C | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7312-IR-C | GT 3C 3#16S PIN PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7312-CV-C | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
| EP7312-CVZ | 功能描述:音頻片上系統(tǒng) - SoC IC Hgh-Prfrmnc Low- Power SOC w/SDRAM RoHS:否 制造商:Cirrus Logic |
| EP7312-CVZ-90 | 功能描述:音頻片上系統(tǒng) - SoC IC Hgh-Prfrmnc Low- Power SOC w/SDRAM RoHS:否 制造商:Cirrus Logic |
| EP7312-CVZR | 功能描述:音頻片上系統(tǒng) - SoC IC Hgh-Prfrmnc Low- Power SOC w/SDRAM RoHS:否 制造商:Cirrus Logic |
| EP7312-EB-90 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM ON CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。