參數(shù)資料
型號: EP7309
廠商: Cirrus Logic, Inc.
英文描述: HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
中文描述: 高性能,低功率片上系統(tǒng)強(qiáng)化數(shù)字音頻接口
文件頁數(shù): 12/46頁
文件大?。?/td> 1893K
代理商: EP7309
12
Copyright 2001 Cirrus Logic (All Rights Reserved)
DS507PP1
EP7309
High-Performance, Low-Power System on Chip
Static Memory
Figure 2
through
Figure 5
define the timings associated with all phases of the Static Memory. The following table
contains the values for the timings of each of the Static Memory modes.
Parameter
Symbol
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
t
CSd
TBD
8
TBD
ns
EXPCLK falling edge to nCS deassert hold time
t
CSh
TBD
4
TBD
ns
EXPCLK rising edge to A assert delay time
t
Ad
TBD
4
TBD
ns
EXPCLK falling edge to A deassert hold time
t
Ah
TBD
8
TBD
ns
EXPCLK rising edge to nMWE assert delay time
t
MWd
TBD
4
TBD
ns
EXPCLK rising edge to nMWE deassert hold time
t
MWh
TBD
4
TBD
ns
EXPCLK falling edge to nMOE assert delay time
t
MOEd
TBD
4
TBD
ns
EXPCLK falling edge to nMOE deassert hold time
t
MOEh
TBD
4
TBD
ns
EXPCLK falling edge to HALFWORD deassert delay time
t
HWd
TBD
4
TBD
ns
EXPCLK falling edge to WORD assert delay time
t
WDd
TBD
4
TBD
ns
EXPCLK rising edge to data valid delay time
t
Dv
TBD
20
TBD
ns
EXPCLK falling edge to data invalid delay time
t
Dnv
TBD
8
TBD
ns
Data setup to EXPCLK falling edge time
t
Ds
TBD
-
TBD
ns
EXPCLK falling edge to data hold time
t
Dh
TBD
-
TBD
ns
EXPCLK rising edge to WRITE assert delay time
t
WRd
TBD
8
TBD
ns
EXPREADY setup to EXPCLK falling edge time
t
EXs
TBD
-
TBD
ns
EXPCLK falling edge to EXPREADY hold time
t
EXh
TBD
-
TBD
ns
相關(guān)PDF資料
PDF描述
EP7309-CB-C CONN MODULAR JACK 8-8 R/A UNSHLD
EP7309-CR-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-CV-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-ER-C HIGH PERFORMANCE LOW POWER SYSTEM ON CHIP ENHANCED DIGITAL AUDIO INTERFACE
EP7309-EV-C CONN MOD JACK 8-8 SHIELD TOP TAB
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