參數(shù)資料
型號(hào): EP7212-CB-A
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述: 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PBGA256
封裝: 17 X 17 MM, 1.53 MM HEIGHT, PLASTIC, BGA-256
文件頁(yè)數(shù): 83/136頁(yè)
文件大小: 2289K
代理商: EP7212-CB-A
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EP7212
DS474PP1
83
5.12
STFCLR Clear all ‘Start Up Reason’ flags location
ADDRESS: 0x8000.05C0
A write to this location will clear all the ‘Start Up Reason’ flags in the system flags status register SYS-
FLG. The ‘Start Up Reason’ flags should first read to determine the reason why the chip was started
(i.e., a new battery was installed). Any value may be written to this location.
5.13
End Of Interrupt Locations
The ‘End of Interrupt’ locations that follow are written to after the appropriate interrupt has been ser-
viced. The write is performed to clear the interrupt status bit, so that other interrupts can be serviced.
Any value may be written to these locations.
5.13.1
BLEOI Battery Low End of Interrupt
ADDRESS: 0x8000.0600
A write to this location will clear the interrupt generated by a low battery (falling edge of BATOK with
nEXTPWR high).
5.13.2
MCEOI Media Changed End of Interrupt
ADDRESS: 0x8000.0640
A write to this location will clear the interrupt generated by a falling edge of the nMEDCHG input pin.
5.13.3
TEOI Tick End of Interrupt Location
ADDRESS: 0x8000.0680
A write to this location will clear the current pending tick interrupt and tick watch dog interrupt.
5.13.4
TC1EOI TC1 End of Interrupt Location
ADDRESS: 0x8000.06C0
A write to this location will clear the under flow interrupt generated by TC1.
13
SMCKEN
: Setting this bit will enable a free running sample clock at twice the programmed ADC
clock frequency to be output on the SMPLCK pin.
TXFRMEN
: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC
configuration field will be shifted out to the ADC and depending on the frame length programmed,
a number of bits will be captured from the ADC. If the SYNCIO register is written to with the
TXFRMEN bit low, no ADC transfer will take place, but the Frame length and SMCKEN bits will
be affected.
ADC Configuration Extension
: When the ADCCON control bit in the SYSCON3 register = 0,
this field is ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the
SYSCON3 register = 1, this field is the configuration data to be sent to the ADC. The ADC Con-
figuration Extension field length is determined by the value held in the ADC Configuration Length
field (SYNCIO[6:0]).
14
16:31
Bit
Description
Table 49. SYNCIO
(cont.)
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