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參數(shù)資料
| 型號： | EP7212-CB-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| 中文描述： | 32-BIT, MROM, 74 MHz, RISC MICROCONTROLLER, PBGA256 |
| 封裝： | 17 X 17 MM, 1.53 MM HEIGHT, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 39/136頁 |
| 文件大?。?/td> | 2289K |
| 代理商： | EP7212-CB-A |
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EP7212
DS474PP1
39
3.13.1
Codec Sound Interface
The codec interface allows direct connection of a
telephony type codec to the EP7212. It provides all
the necessary clocks and timing pulses. It also per-
forms a parallel to serial conversion or vice versa
on the data stream to or from the external codec de-
vice. The interface is full duplex and contains two
separate data FIFOs (16 deep by 8-bits wide, one
for the receive data, another for the transmit data).
Data is transferred to or from the codec at
64 kbits/s. The data is either written to or read from
the appropriate 16-byte FIFO. If enabled, a codec
interrupt (CSINT) will be generated after every
8 bytes are transferred (FIFO half full/empty). This
means the interrupt rate will be every 1 msec, with
a latency of 1 msec.
Transmit and receive modes are enabled by assert-
ing high both the CDENRX and CDENTX codec
enable bits in the SYSCON1 register.
NOTE:
Both the CDENRX and CDENTX enable bits
should be asserted in tandem for data to be
transmitted or received. The reason for this
is that the interrupt generation will occur
1 msec after one of the FIFOs is enabled.
For example: If the receive FIFO gets
enabled first and the transmit FIFO at a later
time, the interrupt will occur 1 msec after the
receive FIFO is enabled. After the first inter-
rupt occurs, the receive FIFO will be half full.
However, it will not be possible to know how
full the transmit FIFO will be since it was
enabled at a later time. Thus, it is possible to
unintentionally overwrite data already in the
transmit FIFO (See
Figure 6
).
After the CDENRX and CDENTX enable bits get
asserted, the corresponding FIFOs become en-
abled. When both FIFOs are disabled, the FIFO sta-
Type
Comments
Referred To As
ADC Interface
SSI2 Interface
DAI Interface
Codec Interface
Max. Transfer Speed
128 kbits/s
512 kbits/s
1.536 Mbits/s
64 kbits/s
SPI / Microwire 1
SPI / Microwire 2
DAI Interface
Codec Interface
Master mode only
Master / slave mode
CD quality DACs and ADCs
Only
for use in the PLL clock mode
Table 21. Serial Interface Options
Pin
No.
LQFP
63
External
Pin Name
SSI2
Slave Mode
(Internal Name)
SSICLK = serial bit
clock; Input
SSKTXFR = TX
frame sync; Input
SSITXDA = TX
data; Output
SSIRXDA = RX
data; Input
SSIRXFR = RX
frame sync; Input
SSI2
Master Mode
Codec
Internal Name
DAI
Internal Name
Strength
SSICLK
Output
PCMCLK =
Output
PCMSYNC = Output
SCLK =
Output
LRCK = Output
1
65
SSITXFR
Output
1
66
SSITXDA
Output
PCMOUT = Output
SDOUT = Output
1
67
SSIRXDA
Input
PCMIN = Input
SDIN = Input
68
SSIRXFR
Output
p/u
(use a 10k pull-up)
MCLK
1
Table 22. Serial-Pin Assignments
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7212-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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