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參數(shù)資料
| 型號： | EP7211-CV-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP208 |
| 封裝： | LQFP-208 |
| 文件頁數(shù)： | 151/166頁 |
| 文件大?。?/td> | 2623K |
| 代理商： | EP7211-CV-A |
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
151
Test Modes
DS352PP3
JUL 2001
Oscillator and PLL Test Mode Signals
defines the EP7211 signal pins used in this test mode. This
mode is only intended to allow test of the oscillators and PLL
.
Note that these inputs are inverted before being passed to the PLL to ensure that the default state of
the port (all zero) maps onto the correct default state of the PLL (
TSEL
= 1,
XTALON
= 1,
PLLON
= 1,
D0
= 0,
D1
= 1,
PLLBP
= 0). This state will produce the correct frequencies as shown in
Table
7-2. Oscillator and PLL Test Mode Signals
. Any other combinations are for testing the oscillator
and PLL and should not be used in-circuit.
7.3
Debug/ICE Test Mode
This mode is selected by
NTEST0
= 0,
NTEST1
= 0, Latched
NURESET
= 1.
Selection of this mode enables the debug mode of the ARM720T. By default, this is disabled which
saves approximately 3% on power.
7.4
Hi-Z (System) Test Mode
This mode selected by
NTEST0
= 0,
NTEST1
= 0, Latched
NURESET
= 0.
This test mode asynchronously disables all output buffers on the EP7211. This has the effect of
removing the EP7211 from the PCB so that other devices on the PCB can be in-circuit tested. The
internal state of the EP7211is not altered directly by this test mode.
7.5
Software Selectable Test Functionality
When Bit 11 of the SYSCON register is set high, internal peripheral bus register accesses are output
on the main address and data buses as though they were external accesses to the address space
addressed by CS5. Hence, CS5 takes on a dual role, it will be active as the strobe for internal accesses
and for any accesses to the standard address range for CS5. Additionally, in this mode, the internal
Table 7-2. Oscillator and PLL Test Mode Signals
Signal
I/O
Pin
Function
TSEL *
I
PA5
PLL test mode
XTLON *
I
PA4
Enable to oscillator circuit
PLLON *
I
PA3
Enable to PLL circuit
PLLBP
I
PA0
Bypasses PLL
RTCCLK
O
COL0
Output of RTC oscillator
CLK1
O
COL1
1 Hz clock from RTC divider chain
OSC36
O
COL2
36 MHz divided PLL main clock
CLK576K
O
COL4
576 KHz divided from above
VREF
O
COL6
Test clock output for PLL
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| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7211-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7212 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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