參數(shù)資料
型號(hào): EP4SE530F43C3NES
廠商: Altera
文件頁數(shù): 61/82頁
文件大?。?/td> 0K
描述: IC STRATIX IV E 530K 1760-FBGA
標(biāo)準(zhǔn)包裝: 3
系列: STRATIX® IV E
LAB/CLB數(shù): 21248
邏輯元件/單元數(shù): 531200
RAM 位總計(jì): 28033024
輸入/輸出數(shù): 1120
電源電壓: 0.87 V ~ 0.93 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
1–56
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
TCCS
True Differential I/O Standards
100
100
100
ps
Emulated Differential I/o
Standards
250
250
250
ps
Receiver
True Differential I/O
Standards -
fHSDRDPA (data rate)
SERDES factor J = 3 to 10 (11)
150
1600
150
1250
150
1250
Mbps
fHSDR (data rate)
SERDES factor J = 3 to 10
Mbps
SERDES factor J = 2,
Uses DDR Registers
Mbps
SERDES factor J = 1,
Uses an SDR Register
Mbps
DPA Mode
DPA run length
10000
10000
10000
UI
Soft CDR mode
Soft-CDR PPM
tolerance
300
300
300
±
PPM
Non DPA Mode
Sampling Window
300
300
300
ps
Notes to Table 1–42:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) For 820, 530, 360, and 290 density devices, the frequency is 762 MHz.
(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local)
that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(6) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the
signal integrity simulation is clean.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(9) This is achieved by using the LVDS and DPA clock network.
(10) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(11) The fMAX specification is based on the fast clock used for serial data. The interface fMAX also depends on the parallel clock domain, which is design
dependent and requires timing analysis.
(12) This only applies to DPA and soft-CDR modes.
(13) This only applies to LVDS source synchronous mode.
Table 1–42. High-Speed I/O Specifications (1), (2) (Part 3 of 3)
Symbol
Conditions
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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EP4SE530F43C4ES 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA
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EP4SE530F43C4NES 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX IV E FPGA 1760FBGA
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