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參數(shù)資料
| 型號： | EP4CGX30CF23I7 |
| 廠商： | Altera |
| 文件頁數(shù)： | 39/42頁 |
| 文件大小： | 0K |
| 描述： | IC CYCLONE IV GX FPGA 30K 484FBG |
| 產(chǎn)品培訓(xùn)模塊： | Cyclone IV FPGA Family Overview |
| 特色產(chǎn)品： | Cyclone? IV FPGAs |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | CYCLONE® IV GX |
| LAB/CLB數(shù)： | 1840 |
| 邏輯元件/單元數(shù)： | 29440 |
| RAM 位總計： | 1105920 |
| 輸入/輸出數(shù)： | 290 |
| 電源電壓： | 1.16 V ~ 1.24 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-FBGA（23x23） |
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1–6
Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
December 2013
Altera Corporation
ESD Performance
This section lists the electrostatic discharge (ESD) voltages using the human body
model (HBM) and charged device model (CDM) for Cyclone IV devices general
purpose I/Os (GPIOs) and high-speed serial interface (HSSI) I/Os. Table 1–5 lists the
ESD for Cyclone IV devices GPIOs and HSSI I/Os.
VCCH_GXB
Transceiver output buffer power supply
—
2.375
2.5
2.625
V
VCCA_GXB
Transceiver PMA and auxiliary power
supply
—
2.375
2.5
2.625
V
VCCL_GXB
Transceiver PMA and auxiliary power
supply
—
1.16
1.2
1.24
V
VI
DC input voltage
—
–0.5
—
3.6
V
VO
DC output voltage
—
0
—
VCCIO
V
TJ
Operating junction temperature
For commercial use
0
—
85
°C
For industrial use
–40
—
100
°C
tRAMP
Power supply ramp time
Standard power
-on reset
(POR) (7)
50 s
—
50 ms
—
Fast POR (8)
50 s
—
3 ms
—
IDiode
Magnitude of DC current across
PCI-clamp diode when enabled
—
——10
mA
Notes to Table 1–4:
(1) All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time.
(2) You must connect VCCD_PLL to VCCINT through a decoupling capacitor and ferrite bead.
(3) Power supplies must rise monotonically.
(4) VCCIO for all I/O banks must be powered up during device operation. Configurations pins are powered up by VCCIO of I/O Banks 3, 8, and 9 where
I/O Banks 3 and 9 only support VCCIO of 1.5, 1.8, 2.5, 3.0, and 3.3 V. For fast passive parallel (FPP) configuration mode, the VCCIO level of I/O
Bank 8 must be powered up to 1.5, 1.8, 2.5, 3.0, and 3.3 V.
(5) You must set VCC_CLKIN to 2.5 V if you use CLKIN as a high-speed serial interface (HSSI) refclk or as a DIFFCLK input.
(6) The CLKIN pins in I/O Banks 3B and 8B can support single-ended I/O standard when the pins are used to clock left PLLs in non-transceiver
applications.
(7) The POR time for Standard POR ranges between 50 and 200 ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended
operating range within 50 ms.
(8) The POR time for Fast POR ranges between 3 and 9 ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended operating
range within 3 ms.
Table 1–4. Recommended Operating Conditions for Cyclone IV GX Devices (Part 2 of 2)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 1–5. ESD for Cyclone IV Devices GPIOs and HSSI I/Os
Symbol
Parameter
Passing Voltage
Unit
VESDHBM
ESD voltage using the HBM (GPIOs) (1)
± 2000
V
ESD using the HBM (HSSI I/Os) (2)
± 1000
V
VESDCDM
ESD using the CDM (GPIOs)
± 500
V
ESD using the CDM (HSSI I/Os) (2)
± 250
V
Notes to Table 1–5:
(1) The passing voltage for EP4CGX15 and EP4CGX30 row I/Os is ±1000V.
(2) This value is applicable only to Cyclone IV GX devices.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP4CGX30CF23I7N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Cyclone IV GX 1840 LABs 290 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4CGX30F17C8 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX30F23C8N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CGX30F23I7N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX50 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
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