參數(shù)資料
型號: EP20K60ERI208-2ES
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 52/114頁
文件大?。?/td> 1623K
代理商: EP20K60ERI208-2ES
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
相關(guān)PDF資料
PDF描述
EP20K60ERI208-3ES FPGA
EP330-25MJB UV-Erasable/OTP PLD
EP330SI-15 UV-Erasable/OTP PLD
EP330-12CFN UV-Erasable/OTP PLD
EP330-12CN UV-Erasable/OTP PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K60ERI208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERI240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERI240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERI240-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ETC144-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 256 Macro 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256