參數(shù)資料
型號(hào): EP20K60ERI208-2ES
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 34/114頁
文件大?。?/td> 1623K
代理商: EP20K60ERI208-2ES
26
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Figure 13. Product-Term Logic in ESB
Note:
(1)
APEX 20KE devices have four dedicated clocks.
Macrocells
APEX 20K macrocells can be configured individually for either sequential
or combinatorial logic operation. The macrocell consists of three
functional blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The product-
term select matrix allocates these product terms for use as either primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
software Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Figure 14 shows the APEX 20K macrocell.
Global Signals
Dedicated Clocks
Macrocell
Inputs (1-16)
CLK[1..0]
ENA[1..0]
CLRN[1..0]
From
Adjacent
LAB
MegaLAB Interconnect
To Row
and Column
Interconnect
2
16
32
2
4
2 or 4
(1)
65
Local
Interconnect
9
相關(guān)PDF資料
PDF描述
EP20K60ERI208-3ES FPGA
EP330-25MJB UV-Erasable/OTP PLD
EP330SI-15 UV-Erasable/OTP PLD
EP330-12CFN UV-Erasable/OTP PLD
EP330-12CN UV-Erasable/OTP PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K60ERI208-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERI240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERI240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ERI240-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K60ETC144-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 256 Macro 92 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256