參數(shù)資料
型號(hào): EP20K400ERI240-2
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PQFP240
封裝: HEAT SINK, POWER, QFP-240
文件頁(yè)數(shù): 48/65頁(yè)
文件大小: 781K
代理商: EP20K400ERI240-2
74
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 33. APEX 20K AC Test Conditions
Operating
Conditions
Tables 15 through 18 provide information on absolute maximum ratings,
recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V APEX 20K devices. Consult Altera for specifications
on 1.8-V APEX 20KE devices.
To Test
System
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
Device
Output
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC conditions.
Large-amplitude, fast-ground-current
transients normally occur as the device
outputs discharge the load capacitances.
When these transients ow through the
parasitic inductance between the device
ground pin and the test system ground,
signicant reductions in observable noise
immunity can result.
Table 15. APEX 20K Device Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage
With respect to ground
–0.5
3.6
V
VCCIO
–0.5
4.6
V
VI
DC input voltage
–2.0
4.6
V
IOUT
DC output current, per pin
–25
25
mA
TSTG
Storage temperature
No bias
–65
150
° C
TAMB
Ambient temperature
Under bias
–65
135
° C
TJ
Junction temperature
PQFP, RQFP, TQFP, and BGA packages,
under bias
135
° C
Ceramic PGA packages, under bias
150
° C
Table 16. APEX 20K Device Recommended Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Min
Max
Unit
VCCINT
Supply voltage for internal logic and
input buffers
2.375
(2.375)
2.625
(2.625)
V
VCCIO
Supply voltage for output buffers, 3.3-V
operation
3.00 (3.00)
3.60 (3.60)
V
Supply voltage for output buffers, 2.5-V
operation
2.30 (2.30)
2.70 (2.70)
V
VI
Input voltage
–0.5
4.1
V
相關(guān)PDF資料
PDF描述
EP20K400ERI240-3 LOADABLE PLD, PQFP240
EP20K400FC672-3X LOADABLE PLD, 3.6 ns, PBGA672
EPB5065G 42 MHz, LOW PASS FILTER
EPC1000P 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
EPC1055PE 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K400FC672-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K400FC672-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA