參數(shù)資料
型號(hào)： EP20K400ERI240-2
廠商： ALTERA CORP
元件分類(lèi)： PLD
英文描述： LOADABLE PLD, PQFP240
封裝： HEAT SINK, POWER, QFP-240
文件頁(yè)數(shù)： 19/65頁(yè)
文件大?。?/td> 781K
代理商： EP20K400ERI240-2
48
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 14. APEX 20K Macrocell
For registered functions, each macrocell register can be programmed
individually to implement D, T, JK, or SR operation with programmable
clock control. The register can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired register type; the
Quartus software then selects the most efficient register operation for each
registered function to optimize resource utilization. The Quartus software
or other synthesis tools can also select the most efficient register operation
automatically when synthesizing HDL designs.
Each programmable register can be clocked by one of two ESB-wide
clocks. The ESB-wide clocks can be generated from device dedicated clock
pins, global signals, or local interconnect. Each clock also has an
associated clock enable, generated from the local interconnect. The clock
and clock enable signals are related for a particular ESB; any macrocell
using a clock also uses the associated clock enable.
If both the rising and falling edges of a clock are used in an ESB, both
ESB-wide clock signals are used.
Clock/
Enable
Select
Product-
Term
Select
Matrix
Parallel Logic
Expanders
(From Other
Macrocells)
ESB-Wide
Clears
ESB-Wide
Clock Enables
ESB-Wide
Clocks
32 Signals
from Local
Interconnect
Clear
Select
ESB
Output
Programmable
Register
2
ENA
D
CLRN
Q
相關(guān)PDF資料
PDF描述
EP20K400ERI240-3 LOADABLE PLD, PQFP240
EP20K400FC672-3X LOADABLE PLD, 3.6 ns, PBGA672
EPB5065G 42 MHz, LOW PASS FILTER
EPC1000P 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
EPC1055PE 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K400FC672-1 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-1ES 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA
EP20K400FC672-1X 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 CPLD - APEX 20K 1664 Macros 502 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400FC672-2ES 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:FPGA
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