參數(shù)資料
型號: EP20K400ERI240-1
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PQFP240
封裝: HEAT SINK, POWER, QFP-240
文件頁數(shù): 56/65頁
文件大?。?/td> 781K
代理商: EP20K400ERI240-1
28
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
All APEX 20K devices are reconfigurable and are 100% tested prior to
shipment. As a result, test vectors do not have to be generated for fault
coverage purposes. Instead, the designer can focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different ASIC designs; APEX 20K devices can be
configured on the board for the specific functionality required.
Table 7. Comparison of APEX 20K & APEX 20KE Features
Feature
APEX 20K Devices
APEX 20KE Devices
MultiCore system integration
Full support
Hot-socketing support
Full support
SignalTap logic analysis
Full support
64-Bit 66-MHz PCI
Full compliance
MultiVolt I/O
2.5-V or 3.3-V VCCIO
VCCIO selected for device
1.8-V, 2.5-V, or 3.3-V VCCIO
VCCIO selected block-by-block
ClockLock support
Clock delay reduction
2
× and 4× clock multiplication
Clock delay reduction
m /(n
× k) clock multiplication
Drive ClockLock output off-chip
External clock feedback
LVDS support
Dedicated clock and input pins Six
Eight
I/O standard support
2.5-V I/O
3.3-V PCI
LVCMOS
LVTTL
1.8-V I/O
2.5-V I/O
3.3-V PCI
3.3-V AGP
CTT
GTL+
HSTL Class I, II, and III
LVCMOS
LVDS (in EP20K300E and larger devices)
LVTTL
SSTL-2 Class I and II
SSTL-3 Class I and II
Memory support
Dual-port RAM
FIFO
RAM
ROM
CAM
Dual-port RAM
FIFO
RAM
ROM
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