參數(shù)資料
型號： EP20K100QC208-3V
廠商： Altera
文件頁數(shù)： 69/117頁
文件大?。?/td> 0K
描述： IC APEX 20K FPGA 100K 208-PQFP
標(biāo)準(zhǔn)包裝： 24
系列： APEX-20K®
LAB/CLB數(shù)： 416
邏輯元件/單元數(shù)： 4160
RAM 位總計： 53248
輸入/輸出數(shù)： 159
門數(shù)： 263000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
Altera Corporation
55
APEX 20K Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All APEX 20K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
APEX 20K devices can also use the JTAG port for configuration with the
Quartus II software or with hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc). Finally, APEX 20K devices use the JTAG port to
monitor the logic operation of the device with the SignalTap embedded
logic analyzer. APEX 20K devices support the JTAG instructions shown in
Table 19. Although EP20K1500E devices support the JTAG BYPASS and
SignalTap instructions, they do not support boundary-scan testing or the
use of the JTAG port for configuration.
Note to Table 19:
(1)
The EP20K1500E device supports the JTAG BYPASS instruction and the SignalTap instructions.
Table 19. APEX 20K JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device
pins. Also used by the SignalTap embedded logic analyzer.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS (1)
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through selected devices to adjacent devices during
normal device operation.
USERCODE
Selects the 32-bit USERCODE register and places it between the TDI and TDO pins,
allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO.
ICR Instructions
Used when configuring an APEX 20K device via the JTAG port with a MasterBlasterTM
or ByteBlasterMVTM download cable, or when using a Jam File or Jam Byte-Code File
via an embedded processor.
SignalTap Instructions
Monitors internal device operation with the SignalTap embedded logic analyzer.
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EP20K100QC240-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100QC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
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EP20K100QC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100QC2403 制造商:Altera 功能描述:_
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