參數(shù)資料
型號: EP20K100QC208-3V
廠商: Altera
文件頁數(shù): 43/117頁
文件大?。?/td> 0K
描述: IC APEX 20K FPGA 100K 208-PQFP
標準包裝: 24
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計: 53248
輸入/輸出數(shù): 159
門數(shù): 263000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
Altera Corporation
31
APEX 20K Programmable Logic Device Family Data Sheet
Figure 18. Deep Memory Block Implemented with Multiple ESBs
The ESB implements two forms of dual-port memory: read/write clock
mode and input/output clock mode. The ESB can also be used for
bidirectional, dual-port memory applications in which two ports read or
write simultaneously. To implement this type of dual-port memory, two
or four ESBs are used to support two simultaneous reads or writes. This
functionality is shown in Figure 19.
Figure 19. APEX 20K ESB Implementing Dual-Port RAM
ESB
to System Logic
Address Decoder
Port A
Port B
address_a[]
address_b[]
data_a[]
data_b[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
相關PDF資料
PDF描述
EP20K100EBI356-2X IC APEX 20KE FPGA 100K 356-BGA
ABB65DHAN CONN EDGECARD 130PS R/A .050 SLD
ABB65DHAD CONN EDGECARD 130PS R/A .050 SLD
ASM31DTAS CONN EDGECARD 62POS R/A .156 SLD
FMC19DREF-S734 CONN EDGECARD 38POS .100 EYELET
相關代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K100QC240-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100QC240-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100QC240-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 416 Macro 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K100QC240-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K100QC2403 制造商:Altera 功能描述:_