Altera Corporation
2–1
June 2006
2. Stratix GX Transceivers
Transceiver
Blocks
Stratix GX devices incorporate dedicated embedded circuitry on the
right side of the device, which contains up to 20 high-speed 3.1875-Gbps
serial transceiver channels. Each Stratix GX transceiver block contains
four full-duplex channels and supporting logic to transmit and receive
high-speed serial data streams. The transceiver block uses the channels to
deliver bidirectional point-to-point data transmissions with up to
3.1875 Gbps of data transition per channel.
There are up to 20 transceiver channels available on a single Stratix GX
device.
Table 2–1 shows the number of transceiver channels available on
each Stratix GX device.
Figure 2–1 shows the elements of the transceiver block, including the four
channels, supporting logic, and I/O buffers. Each transceiver channel
consists of a receiver and transmitter. The supporting logic contains a
transmitter PLL to generate a high-speed clock used by the four
transmitters. The receiver PLL within each transceiver channel generates
the receiver reference clocks. The supporting logic also contains state
machines to manage rate matching for XAUI and GIGE applications, in
addition to channel bonding for XAUI applications.
Table 2–1. Stratix GX Transceiver Channels
Device
Number of Transceiver Channels
EP1SGX10C
4
EP1SGX10D
8
EP1SGX25C
4
EP1SGX25D
8
EP1SGX25F
16
EP1SGX40D
8
EP1SGX40G
20
SGX51002-1.1