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參數(shù)資料
| 型號(hào)： | EP1K50FI484 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484 |
| 文件頁數(shù)： | 5/84頁 |
| 文件大小： | 2224K |
| 代理商： | EP1K50FI484 |
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Altera Corporation
13
Preliminary Information
ACEX 1K Programmable Logic Family Data Sheet
Development
13
Tools
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. The MAX+PLUS II software automatically
combines EABs to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive
write-enable, read-enable, and clock-enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write-enable, read-enable, clear, clock, and clock-enable signals.
An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
to the EAB, has twice as many channels as other columns in the device.
Logic Array Block
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the ACEX 1K architecture, facilitating
efficient routing with optimum device utilization and high performance.
Figure 7 shows the ACEX 1K LAB.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K50FI484-1DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-1F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-1P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-1X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EP1K50FI484-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: |
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