參數(shù)資料
型號: EP1K50FI484
廠商: ALTERA CORP
元件分類: PLD
英文描述: LOADABLE PLD, PBGA484
封裝: 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484
文件頁數(shù): 4/84頁
文件大?。?/td> 2224K
代理商: EP1K50FI484
12
Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable signal. In contrast, the EAB’s synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A circuit using the EAB’s self-timed RAM must only meet the setup
and hold time specifications of the global clock.
When used as RAM, each EAB can be configured in any of the following
sizes: 256
× 16; 512 × 8; 1,024 × 4; or 2,048 × 2. Figure 5 shows the ACEX 1K
EAB memory configurations.
Figure 5. ACEX 1K EAB Memory Congurations
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256
× 16 RAM blocks can be combined to form a 256 × 32
block, and two 512
× 8 RAM blocks can be combined to form a
512
× 16 block. Figure 6 shows examples of multiple EAB combination.
Figure 6. Examples of Combining ACEX 1K EABs
256
× 16
512
× 8
1,024
× 4
2,048
× 2
512
× 8
512
× 8
256
× 16
256
× 16
256
× 32
512
× 16
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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EP1K50FI484-1X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FI484-2 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Altera Corporation 功能描述: