參數(shù)資料
型號(hào): EP1K50FC256-2N
廠商: Altera
文件頁(yè)數(shù): 7/86頁(yè)
文件大?。?/td> 0K
描述: IC ACEX 1K FPGA 50K 256-FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 90
系列: ACEX-1K®
LAB/CLB數(shù): 360
邏輯元件/單元數(shù): 2880
RAM 位總計(jì): 40960
輸入/輸出數(shù): 186
門(mén)數(shù): 199000
電源電壓: 2.375 V ~ 2.625 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FBGA(17x17)
其它名稱(chēng): 544-1841
EP1K50FC256-2N-ND
Altera Corporation
15
ACEX 1K Programmable Logic Device Family Data Sheet
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Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LEs
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the ACEX 1K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
4-input LUT, which is a function generator that can quickly compute any
function of four variables. In addition, each LE contains a programmable
flipflop with a synchronous clock enable, a carry chain, and a cascade
chain. Each LE drives both the local and the FastTrack Interconnect
routing structure. Figure 8 shows the ACEX 1K LE.
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