參數(shù)資料
型號(hào)： EP1K50FC256-2N
廠商： Altera
文件頁(yè)數(shù)： 31/86頁(yè)
文件大小： 0K
描述： IC ACEX 1K FPGA 50K 256-FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 90
系列： ACEX-1K®
LAB/CLB數(shù)： 360
邏輯元件/單元數(shù)： 2880
RAM 位總計(jì)： 40960
輸入/輸出數(shù)： 186
門(mén)數(shù)： 199000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FBGA（17x17）
其它名稱： 544-1841
EP1K50FC256-2N-ND
Altera Corporation
37
ACEX 1K Programmable Logic Device Family Data Sheet
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lo
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13
To
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For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the Altera
software, the GCLK1 pin can feed both the ClockLock and ClockBoost
circuitry in the ACEX 1K device. However, when both circuits are used,
the other clock pin cannot be used.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 19 shows the incoming and generated clock
specifications.
Figure 19. Specifications for the Incoming & Generated Clocks
Note:
(1)
The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock
period.
Input
Clock
ClockLock
Generated
Clock
tCLK1
tINDUTY
tI+ tCLKDEV
tR
tF
tO
tI+ tINCLKSTB
tO
tO tJITTER
tO+ tJITTER
tOUTDUTY
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參數(shù)描述
EP1K50FC256-2P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FC256-2X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
EP1K50FC256-3 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPGA - ACEX 1K 360 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K50FC256-3AA 制造商:Altera Corporation 功能描述:Precision Single, Dual And Quad Rail-to-rail Output Single Supply Amplifiers 制造商:Altera 功能描述:Precision Single, Dual And Quad Rail-to-rail Output Single Supply Amplifiers
EP1K50FC256-3F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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