Notes to tables: (1) All timing paramet" />
參數(shù)資料
型號: EP1K50FC256-2N
廠商: Altera
文件頁數(shù): 62/86頁
文件大?。?/td> 0K
描述: IC ACEX 1K FPGA 50K 256-FBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 90
系列: ACEX-1K®
LAB/CLB數(shù): 360
邏輯元件/單元數(shù): 2880
RAM 位總計: 40960
輸入/輸出數(shù): 186
門數(shù): 199000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應商設備封裝: 256-FBGA(17x17)
其它名稱: 544-1841
EP1K50FC256-2N-ND
Altera Corporation
65
ACEX 1K Programmable Logic Device Family Data Sheet
D
e
ve
lo
pm
e
n
t
13
To
o
ls
Notes to tables:
(1)
All timing parameters are described in Tables 22 through 29 in this data sheet.
(2)
This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(3)
These parameters are specified by characterization.
(4)
This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tables 37 through 43 show EP1K30 device internal and external timing
parameters.
Table 36. EP1K10 External Bidirectional Timing Parameters
Symbol
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
tINSUBIDIR (2)
2.2
2.3
3.2
ns
tINHBIDIR (2)
0.0
ns
tOUTCOBIDIR (2)
2.0
6.6
2.0
7.8
2.0
9.6
ns
tXZBIDIR (2)
8.8
11.2
14.0
ns
tZXBIDIR (2)
8.8
11.2
14.0
ns
tINSUBIDIR (4)
3.1
3.3
tINHBIDIR (4)
0.0
tOUTCOBIDIR (4)
0.5
5.1
0.5
6.4
ns
tXZBIDIR(4)
7.3
9.2
ns
tZXBIDIR (4)
7.3
9.2
ns
Table 37. EP1K30 Device LE Timing Microparameters (Part 1 of 2)
Symbol
Speed Grade
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
tLUT
0.7
0.8
1.1
ns
tCLUT
0.5
0.6
0.8
ns
tRLUT
0.6
0.7
1.0
ns
tPACKED
0.3
0.4
0.5
ns
tEN
0.6
0.8
1.0
ns
tCICO
0.1
0.2
ns
tCGEN
0.4
0.5
0.7
ns
tCGENR
0.1
0.2
ns
tCASC
0.6
0.8
1.0
ns
tC
0.0
ns
tCO
0.3
0.4
0.5
ns
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