參數(shù)資料
型號: EP1K10QC208-2
廠商: Altera
文件頁數(shù): 83/86頁
文件大?。?/td> 0K
描述: IC ACEX 1K FPGA 10K 208-PQFP
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 144
系列: ACEX-1K®
LAB/CLB數(shù): 72
邏輯元件/單元數(shù): 576
RAM 位總計: 12288
輸入/輸出數(shù): 120
門數(shù): 56000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
84
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
During initialization, which occurs immediately after configuration, the
device resets registers, enables I/O pins, and begins to operate as a logic
device. Before and during configuration, all I/O pins (except dedicated
inputs, clock, or configuration pins) are pulled high by a weak pull-up
resistor. Together, the configuration and initialization processes are called
command mode; normal device operation is called user mode.
SRAM configuration elements allow ACEX 1K devices to be reconfigured
in-circuit by loading new configuration data into the device. Real-time
reconfiguration is performed by forcing the device into command mode
with a device pin, loading different configuration data, re-initializing the
device, and resuming user-mode operation. The entire reconfiguration
process requires less than 40 ms and can be used to reconfigure an entire
system dynamically. In-field upgrades can be performed by distributing
new configuration files.
Configuration Schemes
The configuration data for an ACEX 1K device can be loaded with one of
five configuration schemes (see Table 59), chosen on the basis of the target
application. An EPC16, EPC2, EPC1, or EPC1441 configuration device,
intelligent controller, or the JTAG port can be used to control the
configuration of a ACEX 1K device, allowing automatic configuration on
system power-up.
Multiple ACEX 1K devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Additional
APEX 20K, APEX 20KE, FLEX 10K, FLEX 10KA, FLEX 10KE, ACEX 1K,
and FLEX 6000 devices can be configured in the same serial chain.
Device Pin-
Outs
See the Altera web site (http://www.altera.com) or the Altera Documen-
tation Library
for pin-out information.
Table 59. Data Sources for ACEX 1K Configuration
Configuration Scheme
Data Source
Configuration device
EPC16, EPC2, EPC1, or EPC1441 configuration device
Passive serial (PS)
BitBlaster or ByteBlasterMV download cables, or serial data
source
Passive parallel asynchronous (PPA)
Parallel data source
Passive parallel synchronous (PPS)
Parallel data source
JTAG
BitBlaster or ByteBlasterMV download cables, or
microprocessor with a Jam STAPL File or JBC File
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EP1K10QC208-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10QC208-3 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10QC208-3N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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