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參數(shù)資料
| 型號： | EP1K10 |
| 廠商： | Altera Corporation |
| 英文描述： | ACEX 1K Programmable Logic Family(ACEX 1K 系列可編程邏輯) |
| 中文描述： | ACEX一千可編程邏輯系列（ACEX每1000系列可編程邏輯） |
| 文件頁數(shù)： | 6/84頁 |
| 文件大小： | 1366K |
| 代理商： | EP1K10 |
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Altera Corporation
ACEX 1K Programmable Logic Family Data Sheet
Preliminary Information
f
For more information on the configuration of ACEX 1K devices, see the
following documents:
I
I
I
Configuration Devices for APEX & FLEX Devices Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
BitBlaster Serial Download Cable Data Sheet
ACEX 1K devices are supported by the MAX+PLUS II development
system, which is an integrated package that offers schematic, text
(including AHDL), and waveform design entry, compilation and logic
synthesis, full simulation and worst-case timing analysis, and device
configuration. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0,
LPM, VHDL, Verilog HDL, and other interfaces for additional design
entry and simulation support from other industry-standard PC- and
UNIX workstation-based EDA tools.
The MAX+PLUS II software works easily with common gate array EDA
tools for synthesis and simulation. For example, the MAX+PLUS II
software can generate Verilog HDL files for simulation with tools such as
Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains
EDA libraries that use device-specific features such as carry chains, which
are used for fast counter and arithmetic functions. For instance, the
Synopsys Design Compiler library supplied with the MAX+PLUS II
development system includes DesignWare functions that are optimized
for the ACEX 1K device architecture.
The MAX+PLUS II development system runs on Windows-based PCs
and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations.
f
For more information, see the
Development System & Software Data Sheet
.
MAX+PLUS II Programmable Logic
Functional
Description
Each ACEX 1K device contains an enhanced embedded array that
implements memory and specialized logic functions, and a logic array
that implements general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP1K100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Logic Device Family |
| EP1K100FC256-1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP1K100FC256-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 624 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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