參數(shù)資料
型號: EP1K100QI208-2N
廠商: Altera
文件頁數(shù): 55/86頁
文件大?。?/td> 0K
描述: IC ACEX 1K FPGA 100K 208-PQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 144
系列: ACEX-1K®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計(jì): 49152
輸入/輸出數(shù): 147
門數(shù): 257000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 544-1826
EP1K100QI208-2N-ND
Altera Corporation
59
ACEX 1K Programmable Logic Device Family Data Sheet
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To
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Tables 27 through 29 describe the ACEX 1K external timing parameters
and their symbols.
Notes to tables:
(1)
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
(2)
Contact Altera Applications for test circuit specifications and test conditions.
(3)
These timing parameters are sample-tested only.
(4)
This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, Revision 2.2.
Table 27. External Reference Timing Parameters
Symbol
Parameter
Conditions
tDRR
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Table 28. External Timing Parameters
Symbol
Parameter
Conditions
tINSU
Setup time with global clock at IOE register
tINH
Hold time with global clock at IOE register
tOUTCO
Clock-to-output delay with global clock at IOE register
tPCISU
Setup time with global clock for registers used in PCI designs
tPCIH
Hold time with global clock for registers used in PCI designs
tPCICO
Clock-to-output delay with global clock for registers used in PCI designs
Table 29. External Bidirectional Timing Parameters
Symbol
Parameter
Conditions
tINSUBIDIR
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
tINHBIDIR
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
tOUTCOBIDIR
Clock-to-output delay for bidirectional pins with global clock at IOE register
CI = 35 pF
tXZBIDIR
Synchronous IOE output buffer disable delay
CI = 35 pF
tZXBIDIR
Synchronous IOE output buffer enable delay, slow slew rate = off
CI = 35 pF
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EP1K10FC256-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10FC256-1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10FC256-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP1K10FC256-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - ACEX 1K 72 LABs 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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